IS61LV2568
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
Symbol Parameter
-10 ns
Min.
Max.
10
8
8
0
0
7
8
5
0
—
0
—
—
—
—
—
—
—
—
—
4
—
-12 ns
Min. Max.
12
9
9
0
0
8
10
6
0
—
0
—
—
—
—
—
—
—
—
—
5
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ISSI
®
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
1
t
PWE
2
t
SD
t
HD
Write Cycle Time
CE
to Write End
Address Setup Time to
Write End
Address Hold from
Write End
Address Setup Time
WE
Pulse Width (OE = HIGH)
WE
Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
t
HZWE
(3)
WE
LOW to High-Z Output
t
LZWE
(3)
WE
HIGH to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to
3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(CE Controlled,
OE
= HIGH or LOW)
t
WC
ADDRESS
VALID ADDRESS
t
SA
CE
t
SCE
t
HA
WE
t
AW
t
PWE1
t
PWE2
t
HZWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
t
SD
D
IN
t
HD
DATA
IN
VALID
CE_WR1.eps
Note:
1. The internal Write time is defined by the overlap of
CE
= LOW and
WE
= LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/07/03
7
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
