IS61LV2568
AC WAVEFORMS
WRITE CYCLE NO. 2
(1)
(WE Controlled,
OE
= HIGH during Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
ISSI
®
t
HA
OE
CE
LOW
t
AW
t
PWE1
WE
t
SA
D
OUT
DATA UNDEFINED
t
HZWE
HIGH-Z
t
LZWE
t
SD
D
IN
t
HD
DATA
IN
VALID
CE_WR2.eps
Note:
1. The internal Write time is defined by the overlap of
CE
= LOW and
WE
= LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
WRITE CYCLE NO. 3
(WE Controlled:
OE
is LOW During Write Cycle)
t
WC
ADDRESS
VALID ADDRESS
OE
CE
LOW
t
HA
LOW
t
AW
t
PWE2
WE
t
SA
D
OUT
DATA UNDEFINED
t
HZWE
HIGH-Z
t
LZWE
t
SD
D
IN
t
HD
DATA
IN
VALID
CE_WR3.eps
Note:
1. The internal Write time is defined by the overlap of
CE
= LOW and
WE
= LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
02/07/03
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
