IS62C256
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
Symbol
Parameter
Write Cycle Time
-45 ns
Min. Max.
45
35
25
0
0
25
20
0
—
—
—
—
—
—
—
—
-70ns
Min.
Max.
70
60
60
0
0
55
30
0
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ISSI
®
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
CS
to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE
Pulse Width
Data Setup to Write End
Data Hold from Write End
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured
±500
mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CS
LOW and
WE
LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with
OE
HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CS
Controlled,
OE
is HIGH or LOW)
(1 )
t
WC
ADDRESS
VALID ADDRESS
t
SA
CS
t
SCS
t
HA
WE
t
AW
t
PWE1
t
PWE2
t
HZWE
t
LZWE
HIGH-Z
D
OUT
DATA UNDEFINED
t
SD
D
IN
t
HD
DATA
IN
VALID
CS_WR1.eps
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
