IRFR420A, IRFU420A, SiHFR420A,
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
•
Low stray inductance
•
Ground plane
•
Low leakage inductance
current transformer
-
+
-
+
-
R
G
•
•
•
•
dV/dt controlled
by
R
G
Driver same type as D.U.T.
I
SD
controlled
by
duty factor "D"
D.U.T. - device
under
test
+
-
V
DD
Driver gate drive
P.W.
Period
D=
P.W.
Period
V
GS
= 10
V*
D.U.T. I
SD
waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T.
V
DS
waveform
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Inductor current
Body diode forward drop
Ripple
≤
5
%
I
SD
*
V
GS
= 5
V
for logic level devices
Fig. 14 - For N-Channel
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KERSEMI [ Kersemi Electronic Co., Ltd. ]
