ML145050, ML145051
LANSDALE Semiconductor, Inc.
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, Full Temperature and Voltage Ranges per Operation Ranges Table, unless otherwise indicated)
Symbol
VIH
VIL
VOH
VOL
Iin
IOZ
IDD
Iref
IAl
Parameter
Minimum High-Level Input Voltage
(Din, SCLK, CS, ADCLK)
Maximum Low-Level Input Voltage
(Din, SCLK, CS, ADCLK)
Minimum High-Level Output Voltage
(Dout, EOC)
Minimum Low-Level Output Voltage
(Dout, EOC)
Maximum Input Leakage Current
(Din, SCLK, CS, ADCLK)
Maximum Three-State Leakage Current (Dout)
Maximum Power Supply Current
Maximum Static Analog Reference Current (Vref)
Maximum Analog Mux Input Leakage Current between all
deselected inputs and any selected input (AN0
±
AN10)
Iout = – 1.6 mA
Iout = – 20
µA
Iout = + 1.6 mA
Iout = 20
µA
Vin = VSS or VDD
Vout = VSS or VDD
Vin = VSS or VDD, All Outputs Open
Vref = VDD, VAG = VSS
VAl = VSS to VDD
Test Condition
Guaranteed
Limit
2.0
0.8
2.4
VDD – 0.1
0.4
0.1
+
2.5
+
10
2.5
100
+
1
Unit
V
V
V
V
µA
µA
mA
µA
µA
A/D CONVERTER ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table; ML145050: 500 kHz
≤
ADCLK
≤
2.1 MHz, unless otherwise noted)
Characteristic
Resolution
Maximum Nonlinearity
Maximum Zero Error
Maximum Full-Scale Error
Maximum Total Unadjusted Error
Maximum Quantization Error
Absolute Accuracy
Maximum Conversion Time
Definition and Test Conditions
Number of bits resolved by the A/D converter
Maximum difference between an ideal and an actual ADC transfer function
Difference between the maximum input voltage of an ideal and an actual
ADC for zero output code
Difference between the minimum input voltage of an ideal and an actual
ADC for full-scale output code
Maximum sum of nonlinearity, zero error, and full-scale error
Uncertainty due to converter resolution
Difference between the actual input voltage and the full-scale weighted
equivalent of the binary output code, all error sources included
Total time to perform a single analog-to-digital conversion
ML145050
ML145051
Data Transfer Time
Sample Acquisition Time
Minimum Total Cycle Time
Total time to transfer digital serial data into and out of the device
Analog input acquisition time window
Total time to transfer serial data, sample the analog input, and perform the
conversion
ML145050: ADCLK = 2.1 MHz, SCLK = 2.1 MHz
ML145051: SCLK = 2.1 MHz
Rate at which analog inputs may be sampled
ML145050: ADCLK = 2.1 MHz, SCLK = 2.1 MHz
ML145051: SCLK = 2.1 MHz
Guaranteed
Limit
10
±
1
±
1
±
1
±
1
±
1/2
±
1-1/2
44
44
10 to 16
6
Unit
Bits
LSB
LSB
LSB
LSB
LSB
LSB
ADCLK
cycles
µs
SCLK
cycles
SCLK
cycles
µs
26
49
ks/s
38
20.4
Maximum Sample Rate
Page 3 of 15
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