ML145053
LANSDALE Semiconductor, Inc.
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Figure
1
Symbol
f
Clock Frequency, SCLK
Note: Refer to twH, twL below
1
1
1, 7
1, 7
2, 7
2, 7
3
3
4, 7, 8
5
–
–
5
6, 8
1
1, 4, 6 – 8
–
–
twH
twL
tPLH, tPHL
th
tPLZ, tPHZ
tPZL, tPZH
tsu
th
td
tsu
tCSd
tCAs
th
tPHL
tr, tf
tTLH, tTHL
Cin
Cout
Minimum Clock High Time, SCLK
Minimum Clock Low Time, SCLK
Maximum Propagation Delay, SCLK to Dout
Minimum Hold Time, SCLK to Dout
Maximum Propagation Delay, CS to Dout High-Z
Maximum Propagation Delay, CS to Dout Driven
Minimum Setup Time, Din to SCLK
Minimum Hold Time, SCLK to Din
Maximum Delay Time, EOC to Dout (MSB)
Minimum Setup Time, CS to SCLK
Minimum Time Required Between 10th SCLK Falling Edge ( 0.8 V) and
CS to Allow a Conversion
Maximum Delay Between 10th SCLK Falling Edge ( 2 V) and CS to
Abort a Conversion
Minimum Hold Time, Last SCLK to CS
Maximum Propagation Delay, 10th SCLK to EOC
Maximum Input Rise and Fall Times
Maximum Output Transition Time, Any Output
Maximum Input Capacitance
Maximum Three-State Output Capacitance
AN0 – AN4
SCLK, CS, Din
Dout
SCLK
Din, CS
Parameter
(10-bit xfer) Min
(11- to 16-bit xfer) Min
(10- to 16-bit xfer) Max)
Guaranteed
Limit
0
Note 1
2.1
190
190
125
10
150
2.3
100
0
100
2.425
Note 2
9
0
2.35
1
10
300
55
15
15
µs
ns
µs
ms
µs
ns
pF
pF
Unit
MHz
ns
ns
ns
ns
ns
µs
ns
ns
ns
µs
NOTES:
1. After the 10th SCLK falling edge (≥ 2 V), at least 1 SCLK rising edge (≥ 2 V) must occur within 18.5
µs.
2. A CS edge may be received immediately after an active transition on the EOC pin.
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