Specifications GAL16V8
fmax Descriptions
CLK
CLK
LOGIC
ARRAY
REGISTER
LOGIC
ARRAY
t
su
tco
REGISTER
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured
t
cf
pd
tsu and tco.
t
CLK
fmax with Internal Feedback 1/(tsu+tcf)
LOGIC
REGISTER
ARRAY
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
t
su + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels
GAL16V8D-10
GND to 3.0V
2 – 3ns 10% – 90%
+5V
(and slower)
Input Rise
and Fall Times
GAL16V8D-3/-5/-7
1.5ns 10% – 90%
R
1
Input Timing Reference Levels
1.5V
1.5V
See figure at right
Output Timing Reference Levels
Output Load
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
Table 2-0003/16V8
3-state levels are measured 0.5V from
steady-state active level.
C L*
R
2
GAL16V8D (except -3) Output Load Conditions (see figure
above)
Test Condition
R1
R2
CL
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
A
B
200Ω
∞
200Ω
∞
390Ω
390Ω
390Ω
390Ω
390Ω
50pF
50pF
50pF
5pF
Active High
Active Low
Active High
Active Low
C
200Ω
5pF
14
LATTICE [ LATTICE SEMICONDUCTOR ]
