Specifications
GAL18V10
Power-Up Reset
Vcc (min.)
Vcc
t
su
CLK
t
wl
t
pr
INTERNAL REGISTER
Q - OUTPUT
Internal Register
Reset to Logic "0"
ACTIVE LOW
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
ACTIVE HIGH
OUTPUT REGISTER
Device Pin
Reset to Logic "0"
Circuitry within the GAL18V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1µs MAX). As a result,
the state on the registered output pins (if they are enabled) will
be either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be-
cause of the asynchronous nature of system power-up, some
conditions must be met to provide a valid power-up reset of the
device. First, the V
CC
rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of tpr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.
Input/Output Equivalent Schematics
PIN
Feedback
PIN
Vcc
(Vref Typical = 3.2V)
Active Pull-up
Circuit
Active Pull-up
Circuit
Tri-State
Control
Vcc
(Vref Typical = 3.2V)
Vref
Vcc
ESD
Protection
Circuit
Vref
Vcc
PIN
Data
Output
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Typical Input
Typical Output
13
LATTICE [ LATTICE SEMICONDUCTOR ]
