Specifications
GAL20XV10
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the Output Logic
Macrocell. It should be noted that actual implementation is
accomplished by development software/hardware and is com-
pletely transparent to the user.
The GAL20XV10 has two global architecture configurations that
allow it to emulate PAL architectures. The Input mode emulates
combinatorial PAL devices, with the I/CLK and I/OE pins used as
inputs. The Feedback mode emulates registered PAL devices with
the I/CLK pin used as the register clock and the I/OE pin as an
output enable for all registers. The following is a list of PAL archi-
tectures that the GAL20XV10 can emulate. It also shows the
global architecture mode used to emulate the PAL architecture.
PAL Architectures Emulated by
GAL20XV10
PAL12L10
PAL20L10
PAL20X10
PAL20X8
PAL20X4
GAL20XV10 Global
OLMC Mode
Input Mode
Input Mode
Feedback Mode
Feedback Mode
Feedback Mode
Exclusive-OR macrocells. In Feedback mode, the state of the
register is available to the AND array via an internal feedback
path on all macrocells. In Input mode, the state of the register
is available to the AND array via an internal feedback path on
macrocells 2 through 9 only, macrocells 1 and 10 have no feedback
into the AND array.
REGISTERED CONFIGURATION
The Macrocell is set to Registered configuration when AC0 = 1 and
AC1 = 0. Three of the four product terms are used as sum-of-
product terms for the D input of the register. The inverting output
buffer is enabled by the fourth product term. The output is en-
abled while this product term is true. The XOR bit controls the po-
larity of the output. The register is clocked by the low-to-high tran-
sition of the I/CLK. In Feedback mode, the state of the register
is available to the AND array via an internal feedback path on
all macrocells. In Input mode, the state of the register is available
to the AND array via an internal feedback path on macrocells
2 through 9 only, macrocells 1 and 10 have no feedback into the
AND array.
XOR COMBINATORIAL CONFIGURATION
The Macrocell is set to the Exclusive-OR Combinatorial configu-
ration when AC0 = 0 and AC1 = 1. The four product terms are seg-
mented into two OR-sums of two product terms each, which are
then combined by an Exclusive-OR gate and fed to an output
buffer. The inverting output buffer is enabled by the I/OE pin,
which is an active low output enable that is common to all XOR
macrocells. In Feedback mode, the state of the I/O pin is avail-
able to the AND array via an internal feedback path on all
macrocells. In Input mode, the state of the I/O pin is available to
the AND array via an input buffer path on macrocells 2 through
9 only, macrocells 1 and 10 have no input into the AND array.
COMBINATORIAL CONFIGURATION
The Macrocell is set to Combinatorial mode when AC0 = 1 and
AC1 = 1. Three of the four product terms are used as sum-of-
product terms for the combinatorial output. The XOR bit controls
the polarity of the output. The inverting output buffer is enabled
by the fourth product term. The output is enabled while this product
term is true. In Feedback mode, the state of the I/O pin is avail-
able to the AND array via an internal feedback path on all
macrocells. In Input mode, the state of the I/O pin is available
to the AND array via an input buffer path on macrocells 2 through
9 only, macrocells 1 and 10 have no input into the AND array.
INPUT MODE
The Input mode architecture is defined when the global
architecture bit SYN = 1. In this mode, the I/CLK pin becomes an
input to the AND array and also provides the clock source for
all registers. The I/OE pin becomes an input into the AND array
and provides the output enable control for any macrocell config-
ured as an Exclusive-OR function. Feedback into the AND array
is provided from macrocells 2 through 9 only. In this mode,
macrocells 1 and 10 have no feedback into the AND array.
FEEDBACK MODE
The Feedback mode architecture is defined when the global
architecture bit SYN = 0. In this mode the I/CLK pin becomes a
dedicated clock source for all registers. The I/OE pin is a dedi-
cated output enable control for any macrocell configured as an
Exclusive-OR function. The I/CLK and I/OE pins are not avail-
able to the AND array in this mode. Feedback into the AND array
is provided on all macrocells 1 through 10.
FEATURES
Each Output Logic Macrocell has four possible logic function
configurations controlled by architecture control bits AC0 and AC1.
Four product terms are fed into each macrocell.
XOR REGISTERED CONFIGURATION
The Macrocell is set to the Exclusive-OR Registered configuration
when AC0 = 0 and AC1 = 0. The four product terms are seg-
mented into two OR-sums of two product terms each, which are
then combined by an Exclusive-OR gate and fed into a D-type
register. The register is clocked by the low-to-high transition of the
I/CLK pin. The inverting output buffer is enabled by the
I/OE pin, which is an active low output enable common to all
3
LATTICE [ LATTICE SEMICONDUCTOR ]
