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GAL22V10B-25LJ 参数 Datasheet PDF下载

GAL22V10B-25LJ图片预览
型号: GAL22V10B-25LJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 29 页 / 387 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL22V10  
fmax Descriptions  
C L K  
CLK  
LOGIC  
ARRAY  
LOGIC  
ARR AY  
REGISTER  
REGISTER  
t
s u  
tc o  
fmax with External Feedback 1/(tsu+tco)  
t
cf  
pd  
t
Note: fmax with external feedback is cal-  
culated from measured tsu and tco.  
fmax with Internal Feedback 1/(tsu+tcf)  
CLK  
Note: tcf is a calculated value, derived by sub-  
tracting tsu from the period of fmax w/internal  
feedback (tcf = 1/fmax - tsu). The value of tcf is  
used primarily when calculating the delay from  
clocking a register to a combinatorial output  
(through registered feedback), as shown above.  
For example, the timing from clock to a combi-  
natorial output is equal to tcf + tpd.  
LOGIC  
REGISTER  
ARRAY  
t
su + th  
fmax with No Feedback  
Note: fmax with no feedback may be less  
than 1/(twh + twl). This is to allow for a  
clock duty cycle of other than 50%.  
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