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GAL22V10B-25LJ 参数 Datasheet PDF下载

GAL22V10B-25LJ图片预览
型号: GAL22V10B-25LJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用:
文件页数/大小: 29 页 / 387 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications GAL22V10  
Switching Test Conditions  
GAL22V10D-4 Output Load Conditions (see figure below)  
Input Pulse Levels  
GND to 3.0V  
Input Rise and D-4/-5/-7, C-5  
1.5ns 10% 90%  
2.0ns 10% 90%  
Test Condition  
R1  
CL  
Fall Times  
D-10/-15/-20/-25  
B & C-7/-10  
A
50Ω  
50Ω  
50Ω  
50Ω  
50Ω  
50pF  
50pF  
50pF  
50pF  
50pF  
B
Z to Active High at 1.9V  
B-15/-20/-25 3ns  
10% 90%  
1.5V  
Z to Active Low at 1.0V  
Active High to Z at 1.9V  
Active Low to Z at 1.0V  
Input Timing Reference Levels  
Output Timing Reference Levels  
Output Load  
C
1.5V  
See Figure  
3-state levels are measured 0.5V from steady-state active  
level.  
+1.45V  
Output Load Conditions (except D-4) (see figure below)  
TEST POINT  
R1  
Test Condition  
R1  
R2  
CL  
FROM OUTPUT (O/Q)  
UNDER TEST  
A
300Ω  
390Ω  
390Ω  
390Ω  
390Ω  
390Ω  
50pF  
50pF  
50pF  
5pF  
Z0 = 50, CL*  
B
Active High  
Active Low  
Active High  
Active Low  
300Ω  
C
300Ω  
5pF  
+5V  
R
1
FROM OUTPUT (O/Q)  
UNDER TEST  
TEST POINT  
C L*  
R
2
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE  
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