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GAL26CV12C-7LJ 参数 Datasheet PDF下载

GAL26CV12C-7LJ图片预览
型号: GAL26CV12C-7LJ
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能E2CMOS PLD通用阵列逻辑 [High Performance E2CMOS PLD Generic Array Logic]
分类和应用: 可编程逻辑器件输入元件时钟
文件页数/大小: 17 页 / 256 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Specifications
GAL26CV12C
Specifications
GAL26CV12
AC Switching Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
COM
PARAM
TEST
COND.
1
IND
DESCRIPTION
MIN.
Input or I/O to Comb. Output
Clock to Output Delay
Clock to Feedback Delay
Setup Time, Input or Fdbk before Clk
Setup Time, SP before Clock
Hold Time, Input or Fdbk after Clk
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
Maximum Clock Frequency with
No Feedback
Clock Pulse Duration, High
Clock Pulse Duration, Low
Input or I/O to Output Enabled
Input or I/O to Output Disabled
Input or I/O to Asynch. Reset of Reg.
Asynchronous Reset Pulse Duration
Asynch. Reset to Clk↑ Recovery Time
Synch. Preset to Clk
Recovery Time
1
1
6
6
0
95.2
-7
MAX.
7.5
4.5
2.5
-10
MIN. MAX.
1
1
7
7
0
71.4
10
7
2.5
UNITS
ns
ns
ns
ns
ns
ns
MHz
t
pd
t
co
t
cf
2
t
su
1
t
su
2
t
h
A
A
A
f
max
3
A
A
117.6
142.8
105
105
MHz
MHz
t
wh
t
wl
t
en
t
dis
t
ar
t
arw
t
arr
t
spr
B
C
A
3.5
3.5
1
1
1
7
5
5
7.5
7.5
9
4
4
1
1
1
8
8
10
10
9
13
ns
ns
ns
ns
ns
ns
ns
ns
1) Refer to
Switching Test Conditions
section.
2) Calculated from
fmax
with internal feedback. Refer to
fmax Specification
section.
3) Refer to
fmax Specification
section.
Capacitance (T
A
= 25°C, f = 1.0 MHz)
SYMBOL
C
I
C
I/O
PARAMETER
Input Capacitance
I/O Capacitance
MAXIMUM*
8
8
UNITS
pF
pF
TEST CONDITIONS
V
CC
= 5.0V, V
I
= 2.0V
V
CC
= 5.0V, V
I/O
= 2.0V
*Characterized but not 100% tested.
7