Specifications
ispLSI 2032E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
2
4
#
COND.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
B
C
–
–
DESCRIPTION
1
-135
–
–
137
1
-110
–
–
111
77.0
125
5.5
–
0.0
7.5
–
0.0
–
6.5
–
–
–
–
4.0
4.0
10.0
13.0
–
–
–
–
5.5
–
–
6.5
–
12.5
–
14.5
14.5
7.0
7.0
–
–
MIN. MAX. MIN. MAX.
7.5
10.0
–
–
–
–
4.5
–
–
5.5
–
9.0
–
12.0
12.0
6.0
6.0
–
–
UNITS
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
1.
2.
3.
4.
1 Data Propagation Delay, 4PT Bypass, ORP Bypass
2 Data Propagation Delay
3 Clock Frequency with Internal Feedback
3
4 Clock Frequency with External Feedback
(
tsu2 + tco1
)
5 Clock Frequency, Max. Toggle
6 GLB Register Setup Time before Clock, 4 PT Bypass
7 GLB Register Clock to Output Delay, ORP Bypass
8 GLB Register Hold Time after Clock, 4 PT Bypass
9 GLB Register Setup Time before Clock
10 GLB Register Clock to Output Delay
11 GLB Register Hold Time after Clock
12 External Reset Pin to Output Delay, ORP Bypass
13 External Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
100
167
4.0
–
0.0
5.5
–
0.0
–
5.0
–
–
–
–
3.0
3.0
Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
Table 2-0030B/2032E
6
LATTICE [ LATTICE SEMICONDUCTOR ]
