Specifications
ispLSI 2032E
ispLSI 2032E Timing Model
I/O Cell
GRP
Feedback
Ded. In
Comb 4 PT Bypass #23
GRP
#22
Reg 4 PT Bypass
#24
20 PT
XOR Delays
#25, 26, 27
Reset
#45
D
RST
#29, 30,
31, 32
GLB Reg Bypass
#28
GLB Reg
Delay
Q
ORP Bypass
#37
ORP
Delay
#36
#38,
#39
GLB
ORP
I/O Cell
#21
I/O Delay
#20
I/O Pin
(Input)
I/O Pin
(Output)
Control RE
PTs
OE
#33, 34, CK
35
Y0,1,2
GOE 0
#43, 44
#42
#40, 41
0491/2032E
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
t
su
=
=
=
2.7 =
=
=
=
2.3 =
=
=
=
6.8 =
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.6 + 0.7 + 2.2) + (0.8) - (0.6 + 0.7 + 0.3)
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.6 + 0.7 + 2.8) + (1.7) - (0.6 + 0.7 + 2.2)
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.6 + 0.7 + 2.8) + (0.7) + (1.0 + 1.0)
t
h
t
co
Note: Calculations are based upon timing specifications for the ispLSI 2032E-225L
Table 2-0042/2032E
9
LATTICE [ LATTICE SEMICONDUCTOR ]
