Specifications ispLSI 5256VA
Figure 3. ispLSI 5000V Generic Logic Block (GLB)
From Global Routing Pool
0
1
2
6667
Global PTOE Bus
PTSA
PT 0
PT 1
PT 2
PT 3
PT 4
Macrocell 0
From PTSA
PTSA bypass
To I/O Pad
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
To GRP
Global PTOE 0 ... 5
6
PT 9
PT 8
PT 7
PT 6
PT 5
Macrocell 1
From PTSA
PTSA bypass
To I/O Pad
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
To GRP
Global PTOE 0 ... 5
6
PT 79
PT 78
PT 77
PT 76
PT 75
Macrocell 15
From PTSA
PTSA bypass
To I/O Pad
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
To GRP
Global PTOE 0 ... 5
6
PT 159
PT 158
PT 157
PT 156
PT 155
Macrocell 31
From PTSA
PTSA bypass
To I/O Pad
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock 0
Shared PT (P)reset 0
PT 160
PT 161
PT 162
PT 163
Shared PT Clock 1
Shared PT (P)reset 1
To GRP
Global PTOE 0 ... 5
6
PT 164
GLB_5K
Programmable
AND Array
5
LATTICE [ LATTICE SEMICONDUCTOR ]
