Specifications ispLSI 5256VA
speed. The clock inversion is available on the remaining
CLK1 - CLK3 signals. By sharing the pins with the I/O
pins, CLK2 and CLK3 can not only be inverted but also is
available for logic implementation through GRP signal
routing. Figure 5 shows these different clock distribution
options.
Global Clock Distribution
The ispLSI 5000V Family has four dedicated clock input
pins: CLK0 - CLK3. CLK0 input is used as the dedicated
master clock that has the lowest internal clock skew with
no clock inversion to maintain the fastest internal clock
Figure 5. ispLSI 5000V Global Clock Structure
CLK 0
CLK 1
CLK0
CLK1
IO/CLK 2
To GRP
CLK2
CLK3
IO/CLK 3
To GRP
GSET/GRST
SET/RESET
7
LATTICE [ LATTICE SEMICONDUCTOR ]
