Table 8. Register/Latch Operation
1
Configuration
Input(s)
CLK/LE
Q+
D=X
D=0
D=1
0,1, ↓ (↑)
↑ (↓)
Q
0
D-type Register
T-type Register
↑ (↓)
1
T=X
T=0
T=1
0, 1, ↓ (↑)
↑ (↓)
Q
Q
Q
↑ (↓)
D=X
D=0
D=1
1(0)
0(1)
0(1)
Q
0
D-type Latch
1
Note:
1. Polarity of CLK/ LE can be programmed
Although the macrocell shows only one input to the register, the XOR gate in the logic allocator
allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product
terms are divided between J and K (or S and R). When configured as J-K, S-R, or T-type, the
extra product term must be used on the XOR gate input for flip-flop emulation. In any register
type, the polarity of the inputs can be programmed.
The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode,
with the additional choice of either polarity of an individual product term clock in the
asynchronous mode.
The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous
reset and preset are provided, each driven by a product term common to the entire PAL block.
Power-Up
Reset
Power-Up
Preset
PAL-Block
PAL-Block
Initialization
Initialization
Product Terms
Product Terms
AR
Q
AP
D/T/L
AR
Q
AP
D/L
a. Pow er-up reset
b. Pow er-up preset
17466G-012
17466G-013
Figure 7. Synchronous Mode Initialization Configurations
12
ispMACH 4A Family
LATTICE [ LATTICE SEMICONDUCTOR ]
