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M4A5-64/32-10VC 参数 Datasheet PDF下载

M4A5-64/32-10VC图片预览
型号: M4A5-64/32-10VC
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能e 2的CMOS在系统可编程逻辑 [High Performance E 2 CMOS In-System Programmable Logic]
分类和应用: 可编程逻辑
文件页数/大小: 62 页 / 1140 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged,
providing flexibility. In asynchronous mode (Figure 8), a single individual product term is
provided for initialization. It can be selected to control reset or preset.
Power-Up
Reset
Individual
Reset
Product Term
Individual
Preset
Product Term
Power-Up
Preset
AP
D/L/T
AR
Q
AP
D/L/T
AR
Q
a. Reset
17466G-014
b. Preset
17466G-015
Figure 8. Asynchronous Mode Initialization Configurations
Note that the reset/preset swapping selection feature effects power-up reset as well. The
initialization functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data
to the output switch matrix and the input switch matrix. The output switch matrix can route this
data to an output if so desired. The input switch matrix can send the signal back to the central
switch matrix as feedback.
Table 9. Asynchronous Reset/Preset Operation
AR
0
0
1
1
Note:
1. Transparent latch is unaffected by AR, AP
AP
0
1
0
1
CLK/LE
1
X
X
X
X
Q+
See Table 8
1
0
0
ispMACH 4A Family
13