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MACH111-5VC 参数 Datasheet PDF下载

MACH111-5VC图片预览
型号: MACH111-5VC
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能EE CMOS可编程逻辑 [High-Performance EE CMOS Programmable Logic]
分类和应用: 可编程逻辑输入元件时钟
文件页数/大小: 48 页 / 1080 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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The output macrocell (Figure 3) sends its output back to the switch matrix, via internal feedback,
and to the I/O cell. The feedback is always available regardless of the configuration of the I/O cell.
This allows for buried combinatorial or registered functions, freeing up the I/O pins for use as
inputs if not needed as outputs. The basic output macrocell configurations are shown in Figure 4.
The buried macrocell (Figure 5) does not send its output to an I/O cell. The output of a buried
macrocell is provided only as an internal feedback signal which feeds the switch matrix. This
allows the designer to generate additional logic without requiring additional pins. The buried
macrocell can also be used to register or latch inputs. The input register is a D-type flip-flop; the
input latch is a transparent-low D-type latch. Once configured as a registered or latched input, the
buried macrocell cannot generate logic from the product-term array. The basic buried macrocell
configurations are shown in Figure 6.
PAL-Block
Asynchronous
Preset
Sum of Products
from Logic
Allocator
AP
D/T/L
1
Q
1
1
0
0
To I/O
Cell
CLK
0
CLKn
PAL-Block
Asynchronous
Reset
AR
To
Switch
Matrix
14051K-004
Note:
1. Latch option available on MACH 2 devices only.
Figure 3. Output Macrocell
8
MACH 1 & 2 Families