From
Logic
Allocator
n
To
I/O
Cell
From
Logic
Allocator
n
To
I/O
Cell
To Switch
Matrix
a. Combinatorial, active high
To Switch
Matrix
b. Combinatorial, active low
From
Logic
Allocator
CLK0
CLKn
n
D APQ
AR
To
I/O
Cell
From
Logic
Allocator
CLK0
CLKn
n
D AP
Q
AR
To
I/O
Cell
To Switch
Matrix
To Switch
Matrix
c. D-type register, active high
d. D-type register, active low
From
Logic
Allocator
CLK0
CLKn
To Switch
Matrix
n
T AP Q
AR
To
I/O
Cell
From
Logic
Allocator
CLK0
CLKn
n
T AP Q
AR
To
I/O
Cell
To Switch
Matrix
f. T-type register, active low
e. T-type register, active high
From
Logic
Allocator
CLK0
CLKn
To Switch
Matrix
n
L APQ
G
To
I/O
Cell
From
Logic
Allocator
CLK0
n
L APQ
G AR
To
I/O
Cell
AR
CLKn
To Switch
Matrix
g. Latch, active high (MACH 2 only)
h. Latch, active low (MACH 2 only)
14051K-005
Figure 4. Output Macrocell Configurations
MACH 1 & 2 Families
9
LATTICE [ LATTICE SEMICONDUCTOR ]
