Lattice Semiconductor
ispLEVER Development System
ORCA ORT8850 Data Sheet
The ispLEVER development system is used to process a design from a netlist to a configured FPGA. This system
is used to map a design onto the
ORCA
architecture and then place and route it using ispLEVER's timing-driven
tools. The development system also includes interfaces to, and libraries for, other popular CAE tools for design
entry, synthesis, simulation, and timing analysis.
The ispLEVER development system interfaces to front-end design entry tools and provides the tools to produce a
configured FPGA. In the design flow, the user defines the functionality of the FPGA at two points in the design flow,
the design entry and the bit stream generation stage. Recent improvements in ispLEVER allow the user to provide
timing requirement information through logical preferences only; thus, the designer is not required to have physical
knowledge of the implementation.
Following design entry, the development system's map, place, and route tools translate the netlist into a routed
FPGA. A floor planner is available for layout feedback and control. A static timing analysis tool is provided to deter-
mine design speed, and a back-annotated netlist can be created to allow simulation and timing.
Timing and simulation output files from ispLEVER are also compatible with many third-party analysis tools. A bit
stream generator is then used to generate the configuration data which is loaded into the FPGAs internal configu-
ration RAM, embedded block RAM, and/or FPSC memory.
When using the bit stream generator, the user selects options that affect the functionality of the FPGA. Combined
with the front-end tools, ispLEVER produces configuration data that implements the various logic and routing
options discussed in this data sheet.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ispLEVER software and third-party synthesis
and simulation engines, provides all software and documentation required to design and verify an FPSC implemen-
tation. Included in the kit are the FPSC configuration manager,
Synopsys Smart Model
®
, and/or compiled
Verilog
®
simulation model,
HSPICE
®
and/or IBIS models for I/O buffers, and complete online documentation. The kit's soft-
ware couples with ispLEVER software, providing a seamless FPSC design environment. More information can be
obtained by visiting the Lattice website at www.latticesemi.com or contacting a local sales office.
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