Lattice Semiconductor
ORCA ORT8850 Data Sheet
• Meets Universal Test and Operations PHY Interface for ATM (UTOPIA) Levels 1, 2, and 3. Also meets proposed
specifications for UTOPIA Level 4 POS-PHY, Level 3 (2.5 Gbits/s), and POS-PHY 4 (10 Gbits/s) interface stan-
dards for Packet-over-SONET as defined by the Saturn Group.
• ispLEVER development system software. Supported by industry-standard CAE tools for design entry, synthesis,
simulation, and timing analysis.
Description
What is an FPSC?
FPSCs, or Field Programmable System-on-a-Chip devices, are devices that combine field-programmable logic with
ASIC or mask-programmed logic on a single device. FPSCs provide the time to market and the flexibility of FPGAs,
the design effort savings of using soft Intellectual Property (IP) cores, and the speed, design density, and economy
of ASICs.
FPSC Overview
Lattice’s Series 4 FPSCs are created from Series 4
ORCA
FPGAs. To create a Series 4 FPSC, several columns of
Programmable Logic Cells (see FPGA Logic Overview section for FPGA logic details) are added to an embedded
logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efficiency, none of the
FPGA functionality is changed—all of the Series 4 FPGA capability is retained: embedded block RAMs, MPI,
PCMs, boundary scan, etc. Columns of programmable logic are replaced on one side of the device, allowing pins
from the replaced columns to be used as I/O pins for the embedded core. The remainder of the device pins retain
their FPGA functionality.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates.
Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count
is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon-
area efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with
a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to provide a greater number of
interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this
on-chip interface is much faster and requires less power.
Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multi-master
32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic func-
tions including the embedded block RAMs and the MicroProcessor Interface.
Clock spines also can pass across the FPGA/embedded core boundary. This allows fast, low-skew clocking
between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global
set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the
FPGA as a system.
For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This
supports user-programmable options in the embedded core, in turn allowing greater flexibility. Multiple embedded
core configurations may be designed into a single device with user-programmable control over which configura-
tions are implemented, as well as the capability to change core functionality simply by reconfiguring the device.
6
LATTICE [ LATTICE SEMICONDUCTOR ]
