Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0
x
= 0. There is only one registered
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1
x.
The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback
path is from Q on the register. The output buffer is enabled by OE.
Combinatorial Configurations
The PALCE16V8 has three combinatorial output configurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0
x
= 0. All eight product terms are available
to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK
and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin
1 will use the feedback path of MC
7
, and pin 11 will use the feedback path of MC
0
.
Combinatorial I/O in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0
x
= 1. Only seven product terms are
available to the OR gate. The eighth product term is used to enable the output buffer. The signal
at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to
be used as an input.
Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as
inputs. Pin 1 will use the feedback path of MC
7
, and pin 11 will use the feedback path of MC
0
.
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0
x
= 1. Only seven product terms are available
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Dedicated Input Configuration
The control bit settings are SG0 = 1, SG1 = 0 and SL0
x
= 1. The output buffer is disabled. Except
for MC
0
and MC
7
, the feedback signal is an adjacent I/O. For MC
0
and MC
7
, the feedback signals
are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.
U
SE
SG0
SG1
SL0X
Cell
Configuration
G
N AL
EW D
EV
D
ES IC
IG ES
N F
S O
Table 1. Macrocell Configuration
Devices
Emulated
SG0
SG1
SL0X
PAL16R8, 16R6,
16R4
1
0
0
PAL16R6, 16R4
1
0
1
1
1
1
R
Cell
Configuration
Devices
Emulated
Device Uses Registers
0
1
0
Registered Output
Device Uses No Registers
Combinatorial
Output
PAL10H8, 12H6,
14H4, 16H2, 10L8,
12L6, 14L4, 16L2
PAL12H6, 14H4,
16H2, 12L6, 14L4,
16L2
PAL16L8
0
1
1
Combinatorial
I/O
Input
Combinatorial
I/O
4
PALCE16V8 and PALCE16V8Z Families
LATTICE [ LATTICE SEMICONDUCTOR ]
