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PALCE20V8Q-25PC/4 参数 Datasheet PDF下载

PALCE20V8Q-25PC/4图片预览
型号: PALCE20V8Q-25PC/4
PDF下载: 下载PDF文件 查看货源
内容描述: EE CMOS 24引脚通用可编程阵列逻辑 [EE CMOS 24-Pin Universal Programmable Array Logic]
分类和应用: 可编程逻辑器件光电二极管输入元件时钟
文件页数/大小: 27 页 / 500 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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Dedicated Input in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0
x
= 1. The output buffer is disabled. The
feedback signal is an adjacent I/O pin.
Combinatorial I/O in a Non-Registered Device
The control settings are SG0 = 1, SG1 = 1, and SL0
x
= 1. Only seven product terms are available
to the OR gate. The eighth product term is used to enable the output buffer. The signal at the
I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used
as an input.
Combinatorial I/O in a Registered Device
The control bit settings are SG0=0,SG1=1 and SL0
x
=1. Only seven product terms are available
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Table 1. Macrocell Configuration
SG0
SG1
SL0X
Cell
Configuration
Devices
Emulated
SG0
SG1
SL0X
Cell
Configuration
Devices
Emulated
Device Uses Registers
0
0
1
1
0
1
Registered Output
Combinatorial
I/O
PAL20R8, 20R6,
20R4
PAL20R6, 20R4
1
1
1
0
0
1
Device Uses No Registers
0
1
1
Combinatorial
Output
Input
Combinatorial
I/O
PAL20L2, 18L4,
16L6, 14L8
PAL20L2, 18L4, 16L6
PAL20L8
PALCE20V8 Family
5