LT1935
PI FU CTIO S
SW (Pin 1):
Switch Pin. Connect inductor/diode here.
Minimize trace area at this pin to reduce EMI.
GND (Pin 2):
Ground. Tie directly to local ground plane.
FB (Pin 3):
Feedback Pin. Reference voltage is 1.265V.
Connect resistive divider tap here. Minimize trace area at
FB. Set V
OUT
according to V
OUT
= 1.265V(1 + R1/R2).
SHDN (Pin 4):
Shutdown Pin. Tie to 1.8V or more to enable
device. Ground to shut down. This pin also provides a soft-
start function; see Applications Information section.
V
IN
(Pin 5):
Input Supply Pin. Must be locally bypassed.
BLOCK DIAGRA
V
IN
5
A1
FB 3
–
R
C
C
C
SHDN 4
Σ
V
OUT
R1 (EXTERNAL)
FB
R2 (EXTERNAL)
1.2MHz
OSCILLATOR
RAMP
GENERATOR
Figure 2. Block Diagram
OPERATIO
The LT1935 uses a constant frequency, current mode
control scheme to provide excellent line and load regula-
tion. Operation can be best understood by referring to the
Block Diagram in Figure 2. At the start of each oscillator
cycle, the SR latch is set, turning on the power switch Q1.
A voltage proportional to the switch current is added to a
stabilizing ramp and the resulting sum is fed into the
positive terminal of the PWM comparator, A2. When this
voltage exceeds the level at the negative input of A2, the
SR latch is reset, turning off the power switch. The level
at the negative input of A2 is set by error amplifier A1, and
is simply an amplified version of the difference between
the feedback voltage and the reference voltage of 1.265V.
In this manner, the error amplifier sets the correct peak
current level to keep the output in regulation. If the error
amplifier’s output increases, more current is delivered to
the output; if it decreases, less current is delivered. A
clamp on the output of A1 (not shown) limits the switch
current to 3A. A1’s output is also clamped to the voltage
on the SHDN pin, providing a soft-start function by con-
trolling the peak switch current during start-up.
1935f
4
+
–
W
U
U
U
U
1.265V
REFERENCE
+
COMPARATOR
DRIVER
A2
R
S
Q
1 SW
Q1
+
x15
0.01Ω
–
2 GND
1935 BD
LINEAR [ LINEAR INTEGRATED SYSTEMS ]
