LTC2978
PMBus COMMAND DESCRIPTION
MFR_DAC
This command register allows the user to directly program the 1±-bit DAC. Manual DAC writes require the channel to
be in the ON state,TON_RISE to have expired and MFR_CONFIG_LTC2978 b[ꢀ:4] = 1±b or 11b. Writing MFR_CONFIG_
LTC2978 b[ꢀ:4] = 1±b commands the DAC to hard connect with the value in Mfr_dac_direct_val. Writing b[ꢀ:4] = 11b
commands the DAC to soft connect. Once the DAC has soft connected, Mfr_dac_direct_val returns the value that al-
lowed the DAC to be connected without perturbing the power supply.
MFR_DAC Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:1±] Reserved
Read only, always returns ±.
b[9:±] Mfr_dac_direct_val DAC code value.
MFR_POWERGOOD_ASSERTION_DELAY
This command register allows the user to program the delay from when the internal power good signal becomes valid
until the power good output is asserted. This delay is counted using SHARE_CLK if available, otherwise the internal
oscillator is used. This delay is internally limited to 13.1 seconds, and rounded to the nearest 2±±µs. The read value
of this command always returns what was last written and does not reflect internal limiting.
MFR_POWERGOOD_ASSERTION_DELAY Data Contents
BIT(S) SYMBOL
b[1ꢀ:±] Mfr_powergood_assertion_delay The data uses the L11 format.
This delay is counted using SHARE_CLK if available, otherwise the internal oscillator is used.
OPERATION
Delays are rounded to the nearest 2±±µs.
Units: ms. Max delay is 13.1 sec.
WATCHDOG OPERATION
A non zero write to the MFR_WATCHDOG_T register will reset the watchdog timer. Low-to-high transitions on the WDI/
RESETB pin also reset the watchdog timer. If the timer expires, ALERTB is asserted and the PWRGD output is optionally
deassertedandthenreassertedafterMFR_PWRGD_ASSERTION_DELAYms.Writing±toeithertheMFR_WATCH_DOG_T
or MFR_WATCHDOG_T_FIRST registers will disable the timer.
MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T
The MFR_WATCHDOG_T_FIRST register allows the user to program the duration of the first watchdog timer interval
following assertion of the POWER GOOD signal, assuming the POWER GOOD signal reflects the status of the watchdog
timer. If assertion of POWER GOOD is not conditioned by the watchdog timer’s status, then MFR_WATCHDOG_T_FIRST
applies to the first timing interval after the timer is enabled. Writing a value of ±ms to the MFR_WATCHDOG_T_FIRST
register disables the watchdog timer.
The MFR_WATCHDOG_T register allows the user to program watchdog time intervals subsequent to the MFR_
WATCHDOG_T_FIRST timing interval. Writing a value of ±ms to the MFR_WATCHDOG_T register disables the
watchdog timer. A non-zero write to MFR_WATCHDOG_T will reset the watchdog timer.
2978fc
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Linear Systems [ Linear Systems ]
