LTC1062
BLOCK DIAGRA
W
SWITCHED
CAPACITOR
NETWORK
×1
f
CLK
V
–
3
CLOCK GEN
6
V
+
8
B
OUT
7
OUT
÷
1, 2, 4
OSC
5
C
OSC
1062 BD
For Adjusting Oscillator Frequency, Insert a 50k Pot in Series with C
OSC
. Use Two Times Calculated C
OSC
BY CONNECTING PIN 4 TO V
+
, AGND OR V
–
, THE
OUTPUT FREQUENCY OF THE INTERNAL CLOCK
GENERATOR IS THE OSCILLATOR FREQUENCY DI-
VIDED BY 1, 2, 4. THE (f
CLK
/f
C
) RATIO OF 100:1 IS
WITH RESPECT TO THE INTERNAL CLOCK GENERA-
TOR OUTPUT FREQUENCY. PIN 5 CAN BE DRIVEN
WITH AN EXTERNAL CMOS LEVEL CLOCK. THE
LTC1062 CAN ALSO BE SELF-CLOCKED BY CON-
NECTING AN EXTERNAL CAPACITOR (C
OSC
) TO
GROUND (OR TO V
–
IF C
OSC
IS POLARIZED). UNDER
THIS CONDITION AND WITH
±5V
SUPPLIES, THE
INTERNAL OSCILLATOR FREQUENCY IS:
f
OSC
≅
140kHz [33pF/(33pF + C
OSC
)]
FB
1
AGND
2
÷
4
AC TEST CIRCUIT
5V
V
IN
R = 25.8k
C = 0.01µF
50Ω
1
2
FB
AGND
V
–
B
OUT
OUT
V
+
8
7
0.1µF
R′
–5V
5V
5V
–5V
f
CLK
= 100kHz
2
3
+
–
1
7
LTC1052
8
4
6
MEASURED
OUTPUT
FOR BEST MAX FLAT APPROXIMATION,
THE INPUT RC SHOULD BE SUCH AS:
1 = f
CLK
1
•
2πRC 100
1.63
0.1µF
A 0.5k RESISTOR, R′, SHOULD BE USED IF
THE BIPOLAR EXTERNAL CLOCK IS APPLIED
BEFORE THE POWER SUPPLIES TURN ON
LTC1062
V
–
= –5V
3
4
6
5
DIVIDER C
OSC
RATIO
1062 F01
Figure 1
1062fd
5
LINER [ LINEAR TECHNOLOGY ]
