LTC1196/LTC1198
O U
W
U
PPLICATI
A
S I FOR ATIO
Connection to a microprocessor or a DSP serial port is
quite simple (see Data Transfer section). It requires no
additional hardware, but the speed will be limited by the
clock rate of the microprocessor or the DSP which limits
the conversion time of the LTC1196/LTC1198.
conversion result are output on the DOUT line. At the end
of the data exchange CS should be brought high. This
resets the LTC1198 in preparation for the next data ex-
change.
Input Data Word
Data Transfer
The LTC1196 requires no DIN word. It is permanently
configured to have a single differential input. The conver-
sion result is output on the DOUT line in an MSB-first
sequence, followed by zeros indefinitely if clocks are
continuously applied with CS low.
DatatransferdiffersslightlybetweentheLTC1196andthe
LTC1198. The LTC1196 interfaces over 3 lines: CS, CLK
and DOUT. A falling CS initiates data transfer as shown in
the LTC1196 Operating Sequence. After CS falls, the first
CLK pulse enables DOUT. After two null bits, the A/D
conversion result is output on the DOUT line. Bringing CS
high resets the LTC1196 for the next data exchange.
The LTC1198 clocks data into the DIN input on the rising
edge of the clock. The input data word is defined as follows:
SGL/
DIFF
ODD/
SIGN
The LTC1198 can transfer data with 3 or 4 wires. The
additional input, DIN, is used to select the 2-channel MUX
configuration.
DUMMY DUMMY
START
MUX
ADDRESS
DUMMY
BITS
119698 AI02
The data transfer between the LTC1198 and the digital
systemscanbebrokenintotwosections:InputDataWord
and A/D Conversion Result. First, each bit of the input data
word is captured on the rising CLK edge by the LTC1198.
Second, each bit of the A/D conversion result on the DOUT
line is updated on the rising CLK edge by the LTC1198.
This bit should be captured on the next rising CLK edge by
the digital systems (see A/D Conversion Result section).
Start Bit
The first “logical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer. The LTC1198 will ignore all leading zeros which
precede this logical one. After the start bit is received, the
remaining bits of the input word will be clocked in. Further
inputsontheDINpinarethenignoreduntilthenextCScycle.
Multiplexer (MUX) Address
Data transfer is initiated by a falling chip select (CS) signal
as shown in the LTC1198 Operating Sequence. After CS
falls the LTC1198 looks for a start bit. After the start bit is
received, the 4-bit input word is shifted into the DIN input.
ThefirsttwobitsoftheinputwordconfiguretheLTC1198.
ThelasttwobitsoftheinputwordallowtheADCtoacquire
the input voltage by 2.5 clocks before the conversion
starts. After the conversion starts, two null bits and the
The 2 bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the “+” and
“–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND.
CS
LTC1198 Channel Selection
D
D
IN2
IN1
MUX ADDRESS
CHANNEL #
SGL/DIFF ODD/SIGN
0
1
GND
D
D
OUT2
OUT1
1
1
0
0
0
1
0
1
+
–
–
SINGLE-ENDED
MUX MODE
SHIFT MUX
ADDRESS IN
+
–
+
+
–
DIFFERENTIAL
MUX MODE
2 NULL BITS SHIFT A/D CONVERSION
RESULT OUT
1196/98 AI03
1196/98 AI01
15
Linear [ Linear ]
