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LTC1196-2BCS8 参数 Datasheet PDF下载

LTC1196-2BCS8图片预览
型号: LTC1196-2BCS8
PDF下载: 下载PDF文件 查看货源
内容描述: 8位, SO - 8 , 1MSPS ADC,具有自动关机选项 [8-Bit, SO-8, 1MSPS ADCs with Auto-Shutdown Options]
分类和应用: 转换器模数转换器光电二极管
文件页数/大小: 28 页 / 449 K
品牌: Linear [ Linear ]
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LTC1196/LTC1198  
O U  
W
U
PPLICATI  
A
S I FOR ATIO  
Unipolar Output Code  
Dummy Bits  
INPUT VOLTAGE  
(V = 5.000V)  
The last 2 bits of the input word following the MUX  
Address are dummy bits. Either bit can be a “logical  
one” or a “logical zero.” These 2 bits allow the ADC 2.5  
clocks to acquire the input signal after the channel  
selection.  
OUTPUT CODE  
INPUT VOLTAGE  
REF  
4.9805V  
1 1 1 1 1 1 1 1  
V
V
– 1LSB  
REF  
REF  
4.9609V  
1 1 1 1 1 1 1 0  
– 2LSB  
0.0195V  
0V  
0 0 0 0 0 0 0 1  
0 0 0 0 0 0 0 0  
1LSB  
0V  
1196/98 AI05  
A/D Conversion Result  
Both the LTC1196 and the LTC1198 have the A/D  
Operation with DIN and DOUT Tied Together  
conversion result appear on the D  
line after two null  
OUT  
The LTC1198 can be operated with DIN and DOUT tied  
together. This eliminates one of the lines required to  
communicate to the digitalsystems. Data is transmitted in  
both directions on a single wire. The pin of the digital  
systemsconnectedtothisdatalineshouldbeconfigurable  
as either an input or an output. The LTC1198 will take  
control of the data line and drive it low on the 5th falling  
CLK edge after the start bit is received (see Figure 4).  
Therefore the port line of the digital systems must be  
switched to an input before this happens to avoid a  
conflict.  
bits (see Operating Sequence in Figures 1 and 2). Data  
ontheD lineisupdatedontherisingedgeoftheCLK  
OUT  
line. The D  
data should also be captured on the  
OUT  
risingCLKedgebythedigitalsystems.DataontheD  
OUT  
line remains valid for a minimum time of t  
(30ns at  
hDO  
5V) to allow the capture to occur (see Figure 3).  
V
IH  
CLK  
t
dDO  
t
hDO  
V
OH  
D
OUT  
V
OL  
REDUCING POWER CONSUMPTION  
1196/98 TC03  
The LTC1196/LTC1198 can sample at up to a 1MHz rate,  
drawing only 50mW from a 5V supply. Power consump-  
tion can be reduced in two ways. Using a 3V supply lowers  
thepowerconsumptiononbothdevicesbyafactoroffive,  
to 10mW. The LTC1198 can reduce power even further  
because it shuts down whenever it is not converting.  
Figure 5 shows the supply current versus sample rate for  
the LTC1196 and LTC1198 on 3V and 5V. To achieve such  
a low power consumption, especially for the LTC1198,  
several things must be taken into consideration.  
Figure 3. Voltage Waveform for DOUT Delay Time,  
tdDO and thDO  
Unipolar Transfer Curve  
The LTC1196/LTC1198 are permanently configured for  
unipolar only. The input span and code assignment for  
this conversion type are shown in the following figures.  
Unipolar Transfer Curve  
Shutdown (LTC1198)  
1 1 1 1 1 1 1 1  
1 1 1 1 1 1 1 0  
Figure 2 shows the operating sequence of the LTC1198.  
The converter draws power when the CS pin is low and  
powersitselfdownwhenthatpinishigh. Forlowestpower  
consumption in shutdown, the CS pin should be driven  
with CMOS levels (0V to VCC) so that the CS input buffer  
of the converter will not draw current.  
0 0 0 0 0 0 0 1  
0 0 0 0 0 0 0 0  
V
IN  
1196/98 AI04  
16