LTC1771
APPLICATIO S I FOR ATIO
Design Example
As a design example, assume V
IN
= 10V (nominal), V
IN
=
15V
(MAX)
, V
OUT
= 3.3V, and I
MAX
= 2A. With this informa-
tion, we can easily calculate all the important components.
R
SENSE
= 100mV/2A = 0.05Ω
To optimize low current efficiency, MODE pin is tied to V
IN
to enable Burst Mode operation, thus the minimum induc-
tance necessary is:
L
MIN
= 70µH(3.3V + 0.5)(0.05Ω) = 13.3µH
15µH is chosen for the application.
3.3V
+
0.5V
∆
I
L
=
3.5
µ
s
=
0.89A
15
µ
H
For the feedback resistors, choose R1 = 1M to minimize
supply current. R2 can then be calculated to be:
R2 = (V
OUT
/1.23 – 1) • R1 = 1.68M
Assume that the MOSFET dissipation is to be limited to
P
P
= 0.25W.
If T
A
= 70°C and the thermal resistance of the MOSFET is
83°C/W, then the junction temperatures will be 91°C and
δ
P
= 0.33. The required R
DS(ON)
for the MOSFET can now
be calculated:
C
SS
1
C
ITH
R
ITH
2
3
4
RUN/SS
I
TH
V
FB
GND
MODE
SENSE
LTC1771
V
IN
PGATE
8
7
6
5
MODE
R1
R2
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 3. LTC1771 Layout Diagram
+
C
FF
U
P - Channel R
DS(ON)
=
0.25W
3.3V
+
0.5V
2A
10 V
+
0.5V
=
0.130
Ω
W
U U
( ) (
1.33
)
2
Since the gate of the MOSFET will see the full input voltage,
a MOSFET must be selected whose V
GS(MAX)
> 15V. A
P-channel MOSFET that meets both the V
GS(MAX)
and
R
DS(ON)
requirement is the Si6447DQ.
The most stringent requirement for the Schottky diode
occurs when V
OUT
= 0V (i.e., short circuit) at maximum
V
IN
. In this case the worst-case dissipation rises to:
V
IN
P
D
=
I
SC(AVG)
(
V
D
)
V
IN
+
V
D
With a 0.05Ω sense resistor I
SC(AVG)
= 2A will result,
increasing the 0.5V Schottky diode dissipation to 1W.
C
IN
is chosen for a RMS current rating of at least 1A at
temperature. C
OUT
is chosen with an ESR of 0.05Ω for low
output ripple. The output voltage ripple due to ESR is
approximately:
V
ORIPPLE
≈
(R
ESR
)(∆I
L
) = 0.05Ω (0.89A
P-P
) = 45mV
P-P
+
C
IN
D1
Q1
0.1µF
C
OUT
L
V
OUT
1771 F03
11
LINER [ LINEAR TECHNOLOGY ]
