LTC1771
APPLICATIO S I FOR ATIO
between the P-channel MOSFET in series with R
SENSE
and the output diode. The MOSFET R
DS(ON)
plus R
SENSE
multiplied by the duty cycle can be summed with the
resistance of L to obtain I
2
R losses.
4. The catch diode loss is proportional to the forward drop
as the diode conducts current during the off-time and is
more pronounced at high supply voltages where the
off-time is long. However, as discussed in the Catch
Diode section, diodes with lower forward drops often
have higher leakage currents, so although efficiency is
improved, the no-load supply current will increase. The
diode loss is calculated by multiplying the forward
voltage drop times the diode duty cycle multiplied by
the load current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, and inductor core losses, generally account for
less than 2% total additional loss.
Output Voltage Programming
The output voltage is programmed with an external divider
from V
OUT
to V
FB
(Pin 1) as shown in Figure 2. The
regulated voltage is determined by:
R2
V
OUT
=
1.23
1
+
R1
To minimize no-load supply current, resistor values in the
megohm range should be used. The increase in supply
current due to the feedback resistors can be calculated
from:
∆
I
VIN
=
V
OUT
V
OUT
R1
+
R2
V
IN
V
OUT
R2
V
FB
LTC1771
GND
1771 F02
C
FF
5pF
R1
Figure 2. LTC1771 Adjustable Configuaration
U
A 5pF feedforward capacitor across R2 is recommended
to minimize output voltage ripple in Burst Mode operation.
Run/Soft-Start Function
The RUN/SS pin is a dual purpose pin that provides the
soft- start function and a means to shut down the LTC1771.
Soft-start reduces the input surge current from V
IN
by
gradually increasing the internal current limit. Power
supply sequencing can also be accomplished using
this pin.
An internal 1µA current source charges up an external
capacitor C
SS
. When the voltage on the RUN/SS reaches
1V, the LTC1771 begins operating. As the voltage on the
RUN/SS continues to ramp from 1V to 2.2V, the internal
current limit is also ramped at a proportional linear rate.
The current limits begins near 40% maximum load at
V
RUN/SS
= 1V and ends at maximum load at V
RUN/SS
=
2.2V. The output current thus ramps up slowly, reducing
the starting surge current required from the input power
supply. If the RUN/SS has been pulled all the way to
ground, there will be a delay before the current limit starts
increasing and is given by:
t
DELAY
≈
C
SS
/I
CHG
where I
CHG
≅
1µA. Pulling the RUN/SS pin below 0.5V
puts the LTC1771 into a low quiescent current shutdown
(I
Q
< 2µA).
Foldback Current Limiting
As described in the Catch Diode Selection, the worst-case
dissipation for diode occurs with a short-circuit output,
when the diode conducts the current limit value almost
continuously. In most applications this will not cause
excessive heating, even for extended fault intervals. How-
ever, when heat sinking is at a premium or higher forward
voltage drop diodes are being used, foldback current
limiting should be added to reduce the current in propor-
tion to the severity of the fault.
Foldback current limiting is implemented by adding two
diodes in series between the output and the I
TH
pin as
shown in the Functional Diagram. In a hard short (V
OUT
=
0V) the current will be reduced to approximately 25% of
the maximum output current.
W
U U
9
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