L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
DESCRIPTION
The
L7C108
and
L7C109
are high-
performance, low-power CMOS static
RAMs. The storage circuitry is organ-
ized as 131,072 words by 8 bits per
word. The 8 Data In and Data Out
signals share I/O pins. The L7C108 has
a single active-low Chip Enable. The
L7C109 has two Chip Enables (one
active-low). These devices are available
in three speeds with maximum access
times from 10 ns to 15 ns.
Inputs and outputs are TTL compat-
ible. Operation is from a single +5 V
power supply. Power consumption
is 930 mW (typical) at 10 ns. Dissipa-
tion drops to 50 mW (typical) when
the memory is deselected.
consume only 1.5 mW (typical), at 3 V,
allowing effective battery backup
operation.
The L7C108 and L7C109 provide
asynchronous (unclocked) operation
with matching access and cycle times.
The Chip Enables and a three-state I/O
bus with a separate Output Enable
control simplify the connection of
several chips for increased storage
capacity.
Memory locations are specified on
address pins A
0
through A
16
. For the
L7C108, reading from a designated
location is accomplished by presenting
an address and driving CE
1
and OE
LOW while WE remains HIGH. For
the L7C109, CE
1
and OE must be
LOW while CE
2
and WE are HIGH.
The data in the addressed memory
location will then appear on the Data
Out pins within one access time. The
output pins stay in a high-impedance
state when CE
1
or OE is HIGH, or CE
2
(L7C109) or WE is LOW.
Writing to an addressed location is
accomplished when the active-low
CE
1
and WE inputs are both LOW,
and CE
2
(L7C109) is HIGH. Any of
these signals may be used to terminate
the write operation. Data In and Data
Out signals have the same polarity.
Latchup and static discharge protection
are provided on-chip. The L7C108 and
L7C109 can withstand an injection
current of up to 200 mA on any pin
without damage.
FEATURES
q
128K x 8 Static RAM with Chip
Select Powerdown, Output Enable
q
Auto-Powerdown™ Design
q
Advanced CMOS Technology
q
High Speed — to 10 ns maximum
q
Low Power Operation
Active: 570 mW typical at 15 ns
Standby: 5 mW typical
q
Data Retention at 2 V for Battery
Backup Operation
q
DSCC SMD No. 5962-89598
q
Available 100% Screened to
MIL-STD-883, Class B
q
Plug Compatible with Cypress
CY7C108/109, IDT71024/71B024,
Micron MT5C1008, Motorola
MCM6226A/62L26A, Sony
CXK581020
q
Package Styles Available:
• 32-pin Sidebraze, Hermetic DIP
• 32-pin Plastic SOJ
• 32-pin Ceramic LCC
• 32-pin Ceramic SOJ
L7C108/109 B
LOCK
D
IAGRAM
ROW
ADDRESS
O
CE
1
WE
OE
CE
2
(L7C109 only)
BS
O
ROW SELECT
9
Two standby modes are available.
Proprietary Auto-Powerdown™
circuitry reduces power consumption
automatically during read or write
accesses which are longer than the
minimum access time, or when the
memory is deselected. In addition,
data may be retained in inactive
storage with a supply voltage as low
as 2 V. The L7C108 and L7C109
512 x 256 x 8
MEMORY
ARRAY
CONTROL
COLUMN SELECT
& COLUMN SENSE
8
COLUMN ADDRESS
LE
8
I/O
7-0
1
TE
1M Static RAMs
03/04/99–LDS.108/9-N
LODEV [ LOGIC Devices Incorporated ]
