L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
SWITCHING CHARACTERISTICS
Over Operating Range
W
RITE
C
YCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109–
15
Symbol
t
AVAV
t
CLEW
t
AVBW
t
AVEW
t
EWAX
t
WLEW
t
DVEW
t
EWDX
t
WHQZ
t
WLQZ
Parameter
Write Cycle Time
Chip Enable Low to End of Write Cycle
Address Valid to Beginning of Write Cycle
Address Valid to End of Write Cycle
End of Write Cycle to Address Change
Write Enable Low to End of Write Cycle
Data Valid to End of Write Cycle
End of Write Cycle to Data Change
Write Enable High to Output Low Z
(Notes 20, 21)
Write Enable Low to Output High Z
(Notes 20, 21)
Min
15
13
0
13
0
11
8
Max
Min
12
10
0
10
0
9
12
Max
10
Min
10
9
0
9
0
8
5
0
3
5
Max
W
RITE
C
YCLE
— WE C
ONTROLLED
Notes 16, 17, 18, 19
t
AVAV
ADDRESS
t
CLEW
CE
t
AVEW
WE
LE
t
WLEW
t
DVEW
DATA-IN VALID
t
AVBW
DATA IN
O
t
WLQZ
t
PU
t
PU
DATA OUT
HIGH IMPEDANCE
W
RITE
C
YCLE
— CE C
ONTROLLED
Notes 16, 17, 18, 19
t
AVAV
t
CLEW
t
AVEW
t
WLEW
t
DVEW
DATA-IN VALID
ADDRESS
CE
O
BS
t
AVBW
I
CC
WE
DATA IN
DATA OUT
I
CC
HIGH IMPEDANCE
t
PU
t
PD
4
TE
6
0
0
3
3
5
5
t
EWAX
t
EWDX
t
WHQZ
t
PD
t
EWAX
t
EWDX
1M Static RAMs
03/04/99–LDS.108/9-N
LODEV [ LOGIC Devices Incorporated ]
