L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
NOTES
1. Maximum Ratings indicate stress specifi- ments of all parts. Responses from the inter-
cations only. Functional operation of these nal circuitry are specified from the point of
products at values beyond those indicated view of the device. Access time, for ex-
in the Operating Conditions table is not ample, is specified as a maximum since
implied. Exposure to maximum rating con- worst-case operation of any device always
ditions for extended periods may affect re- provides data within that time.
FIGURE 2a.
R
1 480Ω
+5 V
OUTPUT
liability of the tested device.
10. When cascading devices, the reset pulse
R
255Ω
2
2. The products described by this specifica- width must be increased to equal tSLSH +
tion include internal circuitry designed to tSLHH.
30 pF
INCLUDING
JIG AND
SCOPE
protect the chip from damaging substrate
11. It is not recommended that Logic De-
injection currents and accumulations of
vices and other vendor parts be cascaded
static charge. Nevertheless, conventional
together. The parts are designed to be pin-
precautions should be observed during
for-pin compatible but temperature and
storage, handling, and use of these circuits
FIGURE 2b.
voltage compensation may vary from ven-
in order to avoid exposure to excessive elec-
dor to vendor. Logic Devices can only guar-
trical stress values.
R1
480Ω
antee the cascading ofLogicDevices parts to
3. This product provides hard clamping of other Logic Devices parts.
transient undershoot. Input levels below
+5 V
OUTPUT
12. Tested with output open and RS = FL
ground will be clamped beginning at –0.6 V.
= XI = R = W = VCC.
A current in excess of 100 mA is required to
R
255Ω
2
reach –2 V. The device can withstand in-
INCLUDING
JIG AND
SCOPE
5 pF
13. At any given temperature and voltage
condition, output disable time is less than
output enable time for any given device.
definite operation with inputs as low as –3 V
subject only to power dissipation and bond
wire fusing constraints.
14. Transition is measured ±200 mV from
steady state voltage with specified loading
in Fig. 2b. This parameter is sampled and
not 100% tested.
4. “Typical” supply current values are not
shown but may be approximated. At a VCC
of +5.0 V, an ambient temperature of +25°C
and with nominal manufacturing parame-
ters, the operating supply currents will be
approximately 3/ 4 or less of the maximum
values shown.
FIGURE 3.
+3.0 V
90%
10%
<3 ns
15. This product is a very high speed device
and care must be taken during testing in
order to realize valid test information. Inad-
equate attention to setups and procedures
can cause a good part to be rejected as faulty.
Long high-inductance leads that cause sup-
ply bounce must be avoided by bringing the
VCC and ground planes directly up to the
contactor fingers. A 0.01 µF high frequency
capacitor is also required between VCC and
ground. To avoid signal reflections, proper
terminations must be used.
90%
10%
GND
<3 ns
5. Tested with outputs open and data in-
puts changing at the specified read and
write cycle rate. The device is neither full or
empty for the test.
6. Tested with outputs open in the worst
static input control signal combination (i.e.,
W, R, XI, FL, and RS).
7. These parameters are guaranteed but not
100% tested.
8. Test conditions assume input transition
times of 5 ns or less, reference levels of 1.5 V,
output loading for specified IOL and IOH
plus 30 pF (Fig. 2a), and input pulse levels of
0 to 3.0 V (Fig. 3).
9. Each parameter is shown as a minimum
or maximum value. Input requirements are
specified from the point of view of the exter-
nal system driving the chip. For example,
tRLRH is specified as a minimum since the
external system must supply at least that
much time to meet the worst-case require-
OBSOLETE
FIFO Products
03/04/99–LDS.8C201/2/3/4-H
14
LOGIC [ LOGIC DEVICES INCORPORATED ]
