PreLIMINArY INforMAtIoN L9D112G80BG4
1.2 Gb, DDR - SDRAM Integrated Module (IMOD)
Pr e c h a r g e
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank or banks will be available for a
t
subsequent row access a specified time ( RP) after the PRECHARGE command is issued. Except in the case of concurrent auto PRECHARGE, where a
READ or WRITE command to a different bank is allowed as long as it does not violate any other timing parameters. Input A10 determines whether one or all
banks are to be PRECHARGED and in the case where only one bank is to be PRECHARGED, inputs BA0, BA1 select the bank. In all other cases BA0, BA1
are treated as “Don’t Care”. Once a bank has been PRECHARGED, it is in the idle state and must be activated prior to any READ or WRITE commands being
issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the
process of PRECHARGING.
Precharge co m m a n D
CK#
CK
CKE HIGH
CS#
RAS#
CAS#
WE#
Address
All banks
A10
One bank
BA0, BA1
Bank1
Don’t Care
Note:
1. If A10 is HIGH, bank address becomes “Don’t Care.”
au t o Pr e c h a r g e
AUTO PRECHARGE is a feature which performs the same individual bank PRECHARGE function described prior, but without requiring an explicit command.
This is accomplished by using A10 to enable the command/function in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/
row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. AUTO PRECHARGE is
non-persistent in that it is either enabled or disabled for each individual READ or WRITE command. The device supports concurrent AUTO PRECHARGE if
the command to the other bank does not interrupt the data transfer to the current bank.
AUTO PRECHARGE ensures that the PRECHARGE is initiated at the earliest valid stage within a burst. This earliest valid stage is determined as if an explicit
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PRECHARGE command was issued at the earliest possible time without violating RAS (MIN).
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
16
Feb 2, 2009 LDS-L9D112G80BG4-C
LOGIC [ LOGIC DEVICES INCORPORATED ]
