ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
T
ABLE
3 - B
ALL
/S
IGNAL
L
OCATION AND
D
ESCRIPTION
C
ONTINUED
Ball Assignments
G7
Symbol
Type
Description
Input On-Die Termination:
ODT enables (when registered HIGH) and disables termination
resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT
is only applied to each of the following signals: DQ[63:0], LDQSx, LDQSx\, UDQSx,
UDQSx\, UDMx, and LDMx. The ODT input is ignored if disabled via the LOAD MODE
register command. ODT is referenced to VrefCA.
ODT
F3
RESET\
Input RESET:
An input control pin, active LOW referenced to Vss. The RESET\ input receiver
is a CMOS input defined as a rail to rail signal with DC HIGH
≥
0.8 x Vcc and DC LOW
≤
0.2 x VccQ. RESET\ assertion and de-assertion are asynchronous.
D5, C5,
K6, L6
C6, D6,
L5, K5
D2, B3, D4
C2, D7, B8,
D9, B5
B6, B9, D8,
B7, C9, B4,
D3, B2
K2, M3, K4,
L2, K7, M8,
K9, M5
M6, M9, K8,
M7, L9, M4,
K3, M2
A1
LDQSx, LDQSx\
UDQSx, UDQSx\
DQ
0,
DQ
1,
DQ
2,
DQ
3,
DQ
4,
DQ
5,
DQ
6,
DQ
7
DQ
8,
DQ
9,
DQ
10,
DQ
11,
DQ
12,
DQ
13,
DQ
14,
DQ
15
DQ
16,
DQ
17,
DQ
18,
DQ
19,
DQ
20,
DQ
21,
DQ
22,
DQ
23
DQ
24,
DQ
25,
DQ
26,
DQ
27,
DQ
28,
DQ
29,
DQ
30,
DQ
31
unpopulated
Input Data Strobe, LOW Byte (per WORD):
Output, edge-aligned with READ data. Input,
center-aligned with WRITE data.
Input Data Strobe, HIGH Byte (per WORD):
Output, edge-aligned with READ data. Input,
center-aligned with WRITE data.
I/O
Data Input/Output:
LOW Byte, LOW WORD (WORD 1). Pin referenced to VrefDQ.
I/O
Data Input/Output:
HIGH Byte, LOW WORD (WORD 1). Pin referenced to VrefDQ.
I/O
Data Input/Output:
LOW Byte, WORD 2. Pin referenced to VrefDQ.
I/O
Data Input/Output:
HIGH Byte, WORD 2. Pin referenced to VrefDQ.
Unpopulated, un-plated matrix location(s)
LOGIC Devices Incorporated
www.logicdevices.com
9
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
LOGIC [ LOGIC DEVICES INCORPORATED ]
