ADVANCE INFORMATION
L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FUNCTIONAL DESCRIPTION
The DDR3 SDRAM uses double data rate architecture to achieve high
speed operation. The double data rate (DDR) architecture is an 8n prefetch
with an interface designed to transfer two data words per clock cycle at the
I/O pins. A single READ or WRITE access for the DDR3 SDRAM consists
of a single 8n-bit-wide, one-clock-cycle data transfer at the internal memory
core and eight corresponding n-bit-wide, one-half-clock-cycle data transfer
at the I/O pin.
The differential strobes (LDQSx, LDQSx\, UDQSx, UDQSx\) is transmitted
externally, along with data, for use in data capture at the DDR3 SDRAM
input receiver. DQS is center-aligned with data for WRITEs. The READ
data is transmitted by the DDR3 SDRAM and edge-aligned to the data
strobes.
The DDR3 SDRAM operates from a differential clock (CKx, CKx\). The
crossing of CK going HIGH and CK\ going LOW is referred to as the posi-
tive edge of Clock (CK). Control, Command, and Address signals are reg-
istered at every positive edge of CK. Input data is registered on the
first
rising edge of DQS after the WRITE preamble, and output data is refer-
enced on the
first
rising edge of DQS after the READ preamble.
READ and WRITE accesses to the DDR3 SDRAM are burst-oriented.
Accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the
registration of an ACTIVATE command, which is then followed by a READ
or WRITE command. The address bits registered coincident with the ACTI-
VATE command are used to select the bank and the starting column loca-
tion for the burst access.
DDR3 SDRAM devices use READ and WRITE BL8 and BC4. An AUTO
PRECHARGE function may be enabled to provide a self-timed ROW PRE-
CHARGE that is initiated at the end of the burst access.
As with standard DDR SDRAM devices, the pipelined, multi-bank architec-
ture of the DDR3 SDRAM allows for concurrent operation, thereby provid-
ing high bandwidth by hiding ROW PRECHARGE and ACTIVATION time.
A SELF REFRESH mode is provided for all temperature grade offerings
along with AUTO SELF REFRESH for Industrial product, as well as, power-
saving, POWER-DOWN mode.
I
NDUSTRIAL
T
EMPERATURE
The industrial temperature (I) device requires the case temperature not
exceed -40˚C or +85˚C. JEDEC specifications require the REFRESH rate
to double when Tc exceeds +85˚C; this also requires use of the high-
temperature SELF REFRESH option. Additionally, ODT resistance and
the INPUT/OUTPUT impedance must be derated when the Tc is <0˚C or
>+85˚C.
E
XTENDED
T
EMPERATURE
The Extended temperature (E) device requires the case temperature not
exceed -40˚C or +105˚C. JEDEC specifications require the refresh rate
to double when Tc exceeds +85˚C; this also requires use of the high-
temperature SELF REFRESH option. Additionally, ODT resistance and
the INPUT/OUTPUT impedance must be derated when the Tc is <0˚C or
>85˚C.
M
ILITARY
, E
XTREME
O
PERATING
T
EMPERATURE
The Mil-Temp (M) device requires the case temperature not exceed -55˚C
or +125˚C. JEDEC requires the REFRESH rate double when Tc exceeds
+85˚C and LDI recommends an additional derating as specified in this
document as to properly maintain the DRAM core cell charge at tempera-
tures above Tc>105˚C.
LOGIC Devices Incorporated
www.logicdevices.com
5
High Performance, Integrated Memory Module Product
Jul 08, 2009 LDS-L9D320G32BG6-A
LOGIC [ LOGIC DEVICES INCORPORATED ]
