LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
CASO
7-0
— Cascade Output
The data presented on CASO
7-0
is the
internal ALU output delayed by twice
the programmed internal row buffer
length.
Controls
A
2-0
— Control Logic Address Lines
A
2-0
determines which Control Logic
Register will receive the CIN
9-0
data.
CS — Chip Select
When CS is LOW, data can be loaded
into the Control Logic Registers.
When CS is HIGH, data can not be
loaded and the register contents will
not be changed.
LD — Load Strobe
If CS and LD are LOW, the data
present on CIN
9-0
will be latched into
the Control Logic Register addressed
by A
2-0
on the rising edge of LD.
FUNCTIONAL DESCRIPTION
The LF48908, a two-dimensional
convolver, executes convolutions using
internal row buffers to reduce design
complexity and board space require-
ments. 8-bit image data, in raster scan,
non-interlace format, is convolved with
one of two internal, 3 x 3 user-
programable filter kernels. Two 1024 x 8-
bit row buffers provide the data delay
needed to perform two-dimensional
convolutions on a single chip. The result
output of 20-bits allows for word growth
during the convolution operation.
The input data path (DIN
7-0
) provides
access to an 8-bit ALU. This allows
point operations to be performed on
the incoming data stream before
reaching the row buffers and the
convolver. The length of these buffers
is programmable for use in various
video formats without the need for
additional external delay.
This device is configured by loading
the coefficent data (filter kernels) and
row buffer length through the
coefficent data path (CIN
7-0
). Internal
registers are addressed using the A
2-0
address lines. Chip Select (CS) and
Load Strobe (LD) complete the
configuration interface which may be
controlled by standard microproces-
sors without additional external logic.
SIGNAL DEFINITIONS
Power
V
CC
and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers except for the
Control Logic Registers.
Inputs
DIN
7-0
— Pixel Data Input
DIN
7-0
is the 8-bit registered pixel
data input port. Data is latched on the
rising edge of CLK.
CIN
9-0
— Coefficient and Control Logic
Register Input
CIN
7-0
is used to load the Coefficient
Registers or can be used to provide a
second operand input to the ALU.
CIN
8-0
is used to load the Initializa-
tion Register. CIN
9-0
is used to load
the ALU Microcode and Row Buffer
Length Registers. The Control Regis-
ter Address Lines, A
2-0
, determine
which register will receive the CIN
data. The CIN data is loaded into the
addressed register by using the CS
and LD control inputs.
CASI
15-0
— Cascade Input
The cascade input is used when
multiple LF48908s are cascaded
together or when external row buffers
are needed. This allows convolutions
of larger kernels or longer row sizes.
Outputs
DOUT
19-0
— Data Output
DOUT
19-0
is the 20-bit registered data
output port.
1
2
3
4
5
6
7
8
9
10
11
RESET — Reset Control
When RESET is LOW, all internal
circuitry is reset, all outputs are forced
LOW, all Control Logic Registers are
loaded with their default values
(which is 0 for each one except the
ALU Microcode Register which has a
default value of “0000011000”), and all
other internal registers are loaded
with a “0”.
FRAME — New Frame Input Control
When asserted, FRAME signals the
start of a new frame. When FRAME is
LOW, all internal circuitry is reset
except for the ALU Microcode, Row
Length, Initialization, Coefficient, and
ALU Registers.
EALU — Enable ALU Register Input
When HIGH, data on CIN
7-0
is latched
into the ALU Register on the next
rising edge of CLK. When LOW, data
on CIN
7-0
will not be latched into the
ALU Register and the register con-
tents will not be changed.
HOLD — Hold Control
The HOLD input is used to disable
CLK from all of the internal circuitry.
HOLD is latched on the rising edge of
CLK and takes effect on the next rising
edge of CLK. When HOLD is HIGH,
CLK will have no effect on the
LF48908 and all internal data will
remain unchanged.
OE — Output Enable
When OE is LOW, DOUT
19-0
is
enabled for output. When OE is
HIGH, DOUT
19-0
is placed in a high-
impedance state.
Video Imaging Products
3
08/9/2000–LDS.48908-J
LOGIC [ LOGIC DEVICES INCORPORATED ]
