LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
T
ABLE
2. ALU L
OGICAL AND
A
RITHMETIC
O
PERATIONS
ALU MICROCODE REGISTER
REGISTER BIT
T
ABLE
1. ALU S
HIFT
O
PERATIONS
ALU MICROCODE REGISTER
REGISTER BIT
9
0
0
0
0
1
1
1
1
8
0
0
1
1
0
0
1
1
7
0
1
0
1
0
1
0
1
OPERATION
No Shift (Default)
Shift Right 1
Shift Right 2
Shift Right 3
Shift Left 1
Shift Left 2
Shift Left 3
Not Valid
6
0
1
0
0
1
1
0
1
1
5
0
1
0
1
1
0
1
0
0
0
0
1
1
0
1
1
0
1
0
4
0
1
1
0
0
1
1
0
0
0
1
0
1
1
0
1
0
1
0
3
0
1
1
1
0
0
0
1
1
1
0
0
1
1
1
0
0
0
1
2
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
OPERATION
Logical (00000000)
Logical (11111111)
Logical (A) (Default)
Logical (B)
Logical (A)
Logical (B)
Arithmetic (A + B)
Arithmetic (A – B)
Arithmetic (B – A)
Logical (A AND B)
Logical (A AND B)
Logical (A AND B)
Logical (A OR B)
Logical (A OR B)
Logical (A OR B)
Logical (A NAND B)
Logical (A NOR B)
Logical (A XOR B)
Logical (A XNOR B)
Register can hold nine 8-bit values.
This allows two different 3 x 3 filter
kernels to be stored simultaneously on
the LF48908. The outputs of CREG
0
and CREG
1
are connected to the
coefficient inputs of the multiplier
array (A through I). The register used
to supply the coefficient data is
determined by the address written to
the Address Decoder. If a “101” is
written to the Address Decoder,
CREG
0
will provide the coefficient
data. If a “110” is written to the
Address Decoder, CREG
1
will be used.
It is possible to switch between the
two Coefficient Registers in real time.
This facilitates adaptive filtering
operations. It is important to remem-
ber to meet the
t
LCS
timing specifica-
tion when switching the Coefficient
Registers. When a Coefficient Register
is selected to supply data to the
multiplier array (one of the registers is
always selected), all of its outputs are
enabled simultaneously. When RESET
is asserted, CREG
0
is the default
register selected to supply the coeffi-
cient data.
CREG
0
and CREG
1
are loaded
through CIN
7-0
using the A
2-0
, CS, and
LD controls. The nine coefficient
values are presented on CIN
7-0
one by
one, in order from A to I. As each
value is placed on CIN
7-0
, it is latched
into the selected Coefficient Register
using CS and LD. The register to be
0
0
0
0
1
1
1
1
0
1
loaded is determined by the data on
A
2-0
during the load operation. If
CREG
0
is to be loaded, “010” must be
placed on A
2-0
during the load opera-
tion. If CREG
1
is to be loaded, “011”
must be placed on A
2-0
. If desired, the
Coefficient Register that is not being
used to send data to the multiplier
array can be loaded with coefficient
data while the LF48908 is in active
operation.
Address Decoder
The Address Decoder is used to load
the Control Logic Registers and to
determine which Coefficient Register
sends data to the multiplier array. To
load a Control Logic Register, the
address of the register must be placed
on A
2-0
, the data to be written must be
placed on the CIN bus, and CS and
LD must be asserted. The data is
latched into the addressed register
when LD goes HIGH. To select a
Coefficient Register (CREG
0
or
CREG
1
) to send data to the multiplier
array, the appropriate address must be
placed on A
2-0
, and CS and LD must
be asserted. When LD goes HIGH, the
addressed register will begin supply-
ing coefficient data to the multiplier
array. Table 4 lists all of the register
addresses.
The Control Logic Registers can be
modified during active operation of
the LF48908. If this is done, it is very
important to meet the
t
LCS
timing
specification. This is to ensure that the
outputs of the Control Logic Registers
have enough time to change before the
next rising edge of CLK. If
t
LCS
is not
met, unexpected results may occur on
DOUT
19-0
for one clock cycle. There
are two situations in which
t
LCS
may
Video Imaging Products
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08/9/2000–LDS.48908-J
LOGIC [ LOGIC DEVICES INCORPORATED ]
