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Programmable synchronization for deinterleaver, Reed-Solomon
decoder, and descrambler
Bit error monitoring for channel performance measurements
Deinterleaver (DVB and DSS)
Serial host interface compatible with the LSI Logic Serial Control bus
interface
Power-down mode
On-chip dual differential 6-bit ADCs
Supports Synchronous Parallel Interface protocol for FEC data output
Chipset Interconnections
Figure 4
shows the interconnections between the L64733 and L64734.
Figure 4
Chipset Interconnection Diagram
L64733
PLLINn
MODp
MODn
FDOUB
FLCLK
INSEL
AGC1
AGC2
CPG1
CPG2
XTLOUT
PSOUTp
PSOUTn
IOUTp
IOUTn
QOUTp
QOUTn
PLLINp
PLLINn
MODp
MODn
FDOUB
FLCLK
INSEL
AGC1
AGC2
XCTR[0]
XCTR[1]
XOIN
PSOUTp
PSOUTn
IVINp
IVINn
QVINp
QVINn
L64734
Control
Signals
Control
Signals
Prescaler
Signals
Prescaler
Signals
Channel Data
Signals
Channel Data
Signals
L64733/L64734 Tuner and Satellite Receiver Chipset
7
LSI [ LSI COMPUTER SYSTEMS ]
