FIGURE 9A.
LS7060C BLOCK DIAGRAM
CASCADE ENABLE
8
LSB
DATA OUT
MSB
B0 B1 B2 B3 B4 B5 B6 B7
V
DD
V
SS
18
9
+V
-V
5 STATE
STATIC SCAN COUNTER AND
C
SC
DECODER
(STOPS IN STATE 5 UNTIL SCAN RESET
R
SC
CAUSES RESET TO STATE ONE)
ST1
ST2
ST3
ST5
ENABLE
6
5
4
3
17 16 15
14
ENABLE
SCAN
SCAN RESET/LOAD
11
10
12
EN
THREE STATE
OUTPUT DRIVERS
8 BITS
ST4
8 BIT MUX BUS
MUX
GATE
MUX
GATE
MUX
GATE
MUX
GATE
G
G
G
G
LOAD
8 BIT LATCH
LOAD
8 BIT LATCH
LOAD
8 BIT LATCH
LOAD
8 BIT LATCH
B0
COUNT
1
B7
8 BIT BINARY
COUNTER
R
B0
B7
8 BIT BINARY
COUNTER
B0
C
R
B7
8 BIT BINARY
COUNTER
B0
C
R
B7
8 BIT BINARY
COUNTER
C
C
R
2
ALT COUNT
13
7
RESET
TEST COUNT
FIGURE 9B.
LS7061C BLOCK DIAGRAM
CASCADE ENABLE
11
DATA OUT
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
V
DD
V
SS
1
12
+V
-V
14
13
15
9
7
5
3
24
23 20 18
ENABLE
SCAN
SCAN RESET/LOAD
6 STATE
STATIC SCAN COUNTER AND
DECODER
C
SC
(STOPS IN STATE 6 UNTIL SCAN RESET
R
SC
CAUSES RESET TO STATE ONE)
ST1
ST2
ST3
ST4
ST5
ST6
ENABLE
THREE STATE
EN OUTPUT DRIVERS
8 BITS
8 BIT MUX BUS
G
MUX
GATE
G
MUX
GATE
G
MUX
GATE
G
MUX
GATE
G
MUX
GATE
8 BIT LATCH LOAD
LOAD
8 BIT LATCH
LOAD
8 BIT LATCH
LOAD
8 BIT LATCH
LOAD
8 BIT LATCH
B0
C
R
B7
8 BIT BINARY
COUNTER
B0
C
R
B7
8 BIT BINARY
COUNTER
B0
C
R
B7
8 BIT BINARY
COUNTER
B0
C
R
B7
8 BIT BINARY
COUNTER
10
22
19
21
8
17
4
6
RESET
2
16
B0
B2
B4
B6
B1
B3
B5
B7
(COUNT)
TEST COUNT
DATA IN
LSI [ LSI COMPUTER SYSTEMS ]
