®
LY611024
Rev. 1.6
128K X 8 BIT HIGH SPEED CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
V
CC
for Data Retention
SYMBOL
V
DR
TEST CONDITION
CE#
≧
V
CC
- 0.2V
or CE2
≦
0.2V
V
CC
= 2.0V
CE#
≧
V
CC
- 0.2V
Normal
or CE2
≦
0.2V
V
CC
= 2.0V
CE#
≧
V
CC
- 0.2V
LL
or CE2
≦
0.2V
others at 0.2V or V
CC
-0.2V
See Data Retention
Waveforms (below)
MIN.
2.0
-
TYP.
-
0.01
MAX.
5.5
3
UNIT
V
mA
Data Retention Current
I
DR
-
0
t
RC
*
0.5
-
-
30
-
-
µA
ns
ns
Chip Disable to Data
Retention Time
Recovery Time
t
RC
*
= Read Cycle Time
t
CDR
t
R
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1)
(
CE#
controlled)
V
DR
≧
2.0V
Vcc
Vcc(min.)
t
CDR
CE#
V
IH
CE#
≧
Vcc-0.2V
Vcc(min.)
t
R
V
IH
Low Vcc Data Retention Waveform (2)
(CE2 controlled)
V
DR
≧
2.0V
Vcc
Vcc(min.)
t
CDR
CE2
CE2
≦
0.2V
V
IL
V
IL
Vcc(min.)
t
R
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
7
LYONTEK [ Lyontek Inc. ]
