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MRF175GV 参数 Datasheet PDF下载

MRF175GV图片预览
型号: MRF175GV
PDF下载: 下载PDF文件 查看货源
内容描述: N沟道MOS宽带射频功率FET [N-CHANNEL MOS BROADBAND RF POWER FETs]
分类和应用: 晶体晶体管射频放大器局域网
文件页数/大小: 10 页 / 209 K
品牌: MA-COM [ M/A-COM TECHNOLOGY SOLUTIONS, INC. ]
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HANDLING CONSIDERATIONS
The gate of the MOSFET, which is electrically isolated
from the rest of the die by a very thin layer of SiO
2
, may be
damaged if the power MOSFET is handled or installed im-
properly. Exceeding the 40 V maximum gate–to–source volt-
age rating, V
GS(max)
, can rupture the gate insulation and
destroy the FET. RF Power MOSFETs are not nearly as sus-
ceptible as CMOS devices to damage due to static discharge
because the input capacitances of power MOSFETs are
much larger and absorb more energy before being charged
to the gate breakdown voltage. However, once breakdown
begins, there is enough energy stored in the gate–source ca-
pacitance to ensure the complete perforation of the gate ox-
ide. To avoid the possibility of device failure caused by static
discharge, precautions similar to those taken with small–sig-
nal MOSFET and CMOS devices apply to power MOSFETs.
When shipping, the devices should be transported only in
antistatic bags or conductive foam. Upon removal from the
packaging, careful handling procedures should be adhered
to. Those handling the devices should wear grounding straps
and devices not in the antistatic packaging should be kept in
metal tote bins. MOSFETs should be handled by the case
and not by the leads, and when testing the device, all leads
should make good electrical contact before voltage is ap-
plied. As a final note, when placing the FET into the system it
is designed for, soldering should be done with grounded
equipment.
The gate of the power MOSFET could still be in danger af-
ter the device is placed in the intended circuit. If the gate may
see voltage transients which exceed V
GS(max)
, the circuit de-
signer should place a 40 V zener across the gate and source
terminals to clamp any potentially destructive spikes. Using a
resistor to keep the gate–to–source impedance low also
helps damp transients and serves another important func-
tion. Voltage transients on the drain can be coupled to the
gate through the parasitic gate–drain capacitance. If the
gate–to–source impedance and the rate of voltage change
on the drain are both high, then the signal coupled to the gate
may be large enough to exceed the gate–threshold voltage
and turn the device on.
DESIGN CONSIDERATIONS
The MRF176G is a RF power N–channel enhancement
mode field–effect transistor (FETs) designed for VHF and
UHF power amplifier applications. M/A-COM RF MOSFETs
feature a vertical structure with a planar design, thus avoid-
ing the processing difficulties associated with V–groove
MOS power FETs.
M/A-COM Application Note AN211A, FETs in Theory and
Practice, is suggested reading for those not familiar with the
construction and characteristics of FETs.
The major advantages of RF power FETs include high
gain, low noise, simple bias systems, relative immunity from
thermal runaway, and the ability to withstand severely mis-
matched loads without suffering damage. Power output can
be varied over a wide range with a low power dc control sig-
nal, thus facilitating manual gain control, ALC and modula-
tion.
DC BIAS
The MRF176G is an enhancement mode FET and, there-
fore, does not conduct when drain voltage is applied. Drain
current flows when a positive voltage is applied to the gate.
RF power FETs require forward bias for optimum perfor-
mance. The value of quiescent drain current (I
DQ
) is not criti-
cal for many applications. The MRF176G was characterized
at I
DQ
= 100 mA, each side, which is the suggested minimum
value of I
DQ
. For special applications such as linear amplifi-
cation, I
DQ
may have to be selected to optimize the critical
parameters.
The gate is a dc open circuit and draws no current. There-
fore, the gate bias circuit may be just a simple resistive divid-
er network. Some applications may require a more elaborate
bias system.
GAIN CONTROL
Power output of the MRF176G may be controlled from its
rated value down to zero (negative gain) by varying the dc
gate voltage. This feature facilitates the design of manual
gain control, AGC/ALC and modulation systems.
REV 9
9