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    88EM8040 参数 Datasheet PDF下载

    88EM8040图片预览
    型号： 88EM8040
    PDF下载： 下载PDF文件 查看货源
    内容描述： 功率因数校正控制器的反激式拓扑结构 [Power Factor Correction Controller for Flyback Topology]
    分类和应用： 功率因数校正控制器
    文件页数/大小： 48 页 / 445 K
    品牌： MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
     浏览型号88EM8040的Datasheet PDF文件第3页浏览型号88EM8040的Datasheet PDF文件第4页浏览型号88EM8040的Datasheet PDF文件第5页浏览型号88EM8040的Datasheet PDF文件第6页浏览型号88EM8040的Datasheet PDF文件第8页浏览型号88EM8040的Datasheet PDF文件第9页浏览型号88EM8040的Datasheet PDF文件第10页浏览型号88EM8040的Datasheet PDF文件第11页  
    List of Figures
    List of Figures
    Figure 1:
    PFC Flyback Circuit Diagram ............................................................................................................3
    1
    Signal Description ........................................................................................................................... 11
    Figure 2:
    SOIC-8 Pin Diagram (Top View).......................................................................................................11
    2
    3
    Electrical Specifications ................................................................................................................. 13
    Functional Description.................................................................................................................... 19
    Figure 3:
    Top Level Block Diagram..................................................................................................................19
    4
    Functional Characteristics.............................................................................................................. 21
    Figure 4:
    Figure 5a:
    Figure 5b:
    Figure 6a:
    Figure 6b:
    Figure 7:
    Figure 8:
    Figure 9:
    Figure 10:
    Figure 11:
    Figure 12:
    Figure 13:
    Figure 14:
    Figure 15:
    Figure 16:
    I
    DD
    Quiescent (IDD_QST) vs. V
    DD
    ...................................................................................................21
    I
    DD
    vs. V
    DD
    (V
    DD_ON
    ) ........................................................................................................................21
    I
    DD
    vs. V
    DD
    (V
    DD_ON
    )........................................................................................................................21
    I
    DD
    Operation (IDD_OP) vs. Temperature ........................................................................................22
    I
    DD
    Operation (IDD_OP) vs. Temperature ........................................................................................22
    VDD On/Off vs. Temperature ...........................................................................................................22
    I
    DD
    vs. V
    FB
    (OVP) .............................................................................................................................23
    VFB_OVP vs. Temperature ..............................................................................................................23
    VFB_OVP Hysteresis vs. Temperature ............................................................................................23
    VFB_OVP_LATCH vs. Temperature ................................................................................................23
    Normal Regulation Reference (VFB_REG) vs. Temperature ...........................................................24
    Switching Frequency vs. Temperature .............................................................................................24
    Over Current (VIOVER) vs. Input Voltage VIN Peak Value).............................................................25
    Over Current (VIOVER) vs. Temperature .........................................................................................25
    VIOVER_CYC_ON/OFF vs. Temperature ........................................................................................26
    5
    Design and Applications Information ............................................................................................ 27
    Figure 17:
    Figure 18:
    Figure 19:
    Figure 20:
    Figure 21:
    Figure 22:
    Figure 23:
    Figure 24:
    Figure 25:
    Figure 26:
    Figure 27:
    Figure 28:
    Internal Block for Zero-cross Detection, Brown-out Protection .........................................................28
    Peak Detecting Signal for Predictive Sinusoidal AC Voltage............................................................29
    Input Voltage Resistor Divider Layout Guidelines ............................................................................30
    Secondary Compensation Network with Opt-coupler .......................................................................30
    Bode Plot of Compensation Network at Secondary Side .................................................................32
    Bias Current for Offset Voltage on FB Pin ........................................................................................33
    Current Sensing Circuit.....................................................................................................................34
    Current Sensing and Cycle by Cycle Over Current Protection Circuit ..............................................36
    Current Sensing and Cycle by Cycle Over Current Protection Waveforms ......................................36
    SW Pin Layout Guidelines ................................................................................................................39
    VDD Decoupling Capacitor and Ground Layout Guidelines .............................................................40
    90W/20V Single Stage PFC Adaptor Schematic ..............................................................................41
    Copyright © 2009 Marvell
    October 5, 2009, Preliminary
    Document Classification: Proprietary
    Doc. No. MV-S104983-01 Rev. A
    Page 7

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