Pin and Signal Descriptions
Pin Descriptions
1.2.17
Precise Timing Protocol (PTP) Interface
Note
All of the PTP signals are multiplexed on the MPP pins (see
).
Table 19: Precise Timing Protocol (PTP) Interface Signal Assignment
Pin Name
I/O
Pin Type
Power Rail
Description
PTP_CLK
PTP_EVENT_REQ
PTP_TRIG_GEN
I
I
O
CMOS
CMOS
CMOS
VDDO
VDDO
VDDO
PTP Clock
Trigger generation to the PTP core.
Trigger generated by the PTP core.
Copyright © 2008 Marvell
December 2, 2008, Preliminary
Document Classification: Proprietary Information
Doc. No. MV-S104988-U0 Rev. E
Page 37