Pin Multiplexing
Multi-Purpose Pins Functional Summary
4
4.1
Pin Multiplexing
Multi-Purpose Pins Functional Summary
The 88F6180 device contains 30 Multi-Purpose Pins (MPP)—MPP[19:0] and MPP[44:35]. The MPP
range is not consecutive. Each one can be assigned to a different functionality through the MPP
Control register.
General Purpose pins: MPP[5:0], MPP[19:7], and MPP[44:35]:
•
GPIO (input/output): MPP[0], MPP[4], MPP[9:8], MPP[9], MPP[11], MPP[17:13], and
MPP[44:35]
•
GPO (output): MPP[3:1], MPP[5], MPP[7], MPP[10], MPP[12], and MPP[19:18]
SYSRST_OUTn: Reset request from the device to the board reset logic. This pin is an output.
SYSRST_OUTn is the default setting for MPP[6].
PEX_RST_OUTn: Optional PCI Express Endpoint card reset output.
NF_IO[7:0] (NAND Flash data [7:0])
SPI interface: SPI_MOSI, SPI_MISO, SPI_SCK, SPI_CSn
UART interface: Transmit and receive functions: UA0/1_TXD, UA0/1_RXD, and Modem control
functions: UA0/1_RTSn, UA0/1_CTSn
SDIO interface: SD_CLK, SD_CMD, SD_D[3:0]
Audio interface signals: AU_SPDIFI, AU_SPDIFO, AU_SPDIFRMCLK, AU_I2SBCLK,
AU_I2SDO, AU_I2SLRCLK, AU_I2SMCLK, AU_I2SDI, AU_EXTCLK
PTP signals: PTP_EVENT_REQ, PTP_TRIG_GEN, PTP_CLK
TWSI signals: TW_SDA, TW_SCK
MPP pins can be assigned to different functionalities through the MPP Control register (see
Table 22: MPP Functionality
MPP[19:0]
GPIO
NAND flash
TWSI
UART
SPI
PTP
SDIO
MPP[44:35]
GPIO
Audio
MII
lists the functionality of the MPP pins, as determined by the MPP Multiplex register, see the
Pins Multiplexing Interface Registers section in the
88F6180, 88F6190, 88F6192, and 88F6281
Functional Specifications.
Copyright © 2008 Marvell
December 2, 2008, Preliminary
Document Classification: Proprietary Information
Doc. No. MV-S104988-U0 Rev. E
Page 41
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
