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MAS6180A2TC05 参数 Datasheet PDF下载

MAS6180A2TC05图片预览
型号: MAS6180A2TC05
PDF下载: 下载PDF文件 查看货源
内容描述: AM接收器IC [AM Receiver IC]
分类和应用:
文件页数/大小: 9 页 / 128 K
品牌: MAS [ MICRO ANALOG SYSTEMS ]
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DA6180.001
27 December, 2006
MAS6180 PAD LAYOUT
VSS pad
bonded
first!
1070
µ
m
VDD
QOP
QOM
QI
AGC
OUT
VSS
RFIM
RFIP
PDN
AON
DEC
MAS6180Ax,
x = 1, 2, 5
DIE size = 1.07 mm x 1.37 mm; PAD size = 80
µm
x 80
µm
Note:
Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left
floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly
are recommended to be performed in ESD protected area.
Note:
Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.
Pad Identification
Power Supply Voltage
Positive Quartz Filter Output for Crystal
Negative Quartz Filter Output for Crystal
Quartz Filter Input for Crystal and External
Compensation Capacitor
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down
Positive Receiver Input
Negative Receiver Input
Power Supply Ground
Name
VDD
QOP
QOM
QI
AGC
OUT
DEC
AON
PDN
RFIP
RFIM
VSS
X-coordinate
152
µm
152
µm
152
µm
152
µm
152
µm
152
µm
915
µm
915
µm
915
µm
915
µm
915
µm
915
µm
Y-coordinate
1137
µm
1002
µm
815
µm
629
µm
443
µm
257
µm
265
µm
451
µm
636
µm
824
µm
1010
µm
1158
µm
Note
1370
µ
m
1
2
3
4
5
5
Notes:
1) External crystal compensation capacitor pin QOM is connected only in MAS6180A5 version. It is left
unconnected in MAS6180A1 and A2 versions which have internal compensation capacitor.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
-
the output is a current source/sink with |I
OUT
| > 5
µA
-
at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
-
Internal pull-up with current < 1
µA
which is switched off at power down
4) PDN = VSS means receiver on; PDN = VDD means receiver off
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
5) Receiver inputs RFIP and RFIM have both 600 kΩ biasing resistors towards VDD
2 (9)