Low Voltage 8 Megabit (256K x 32-Bit) EEPROM MCM
79LV0832
high for 100µ s after data input, the EEPROM enters the write mode automatically and the data input is written into the
EEPROM.
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of
WE or CE.
Data Polling
Data Polling function allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a
write cycle, an inversion of the last dword of data to be loaded outputs from I/O 7, 15, 23, 31 to indicate that the
EEPROM is performing a write operation.
RDY/Busy Signal
RDY/Busy signal also allows a comparison operation to determine the status of the EEPROM. The RDY/Busy signal
goes low (V
OL)
after the first write signal. At the end of the write cycle, the RDY/Busy returns to a high state ( V
OH
).
RES Signal
Memory
When RES is LOW (V
L
), the EEPROM cannot be read or programmed. The EEPROM data must be protected by
keeping RES low when V
CC
is power on and off. RES should be high (V
H
) during read and programming operations.
Data Protection
To protect the data during operation and power on/off, the EEPROM has the internal functions described below.
1. Data Protection at V
CC
on/off
When V
CC
is turned on or off, noise on the control pins generated by external circuits, such as CPUs, may turn the EEPROM to
programming mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable
state during V
CC
on/off by using a CPU reset signal to RES pin.
01.10.05 Rev 8
All data sheets are subject to change without notice
13
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