MX25L1605D
MX25L3205D
MX25L6405D
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for more
details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current.
The MX25L1605D/3205D/6405D utilizes MXIC's proprietary memory cell, which reliably stores memory contents even
after typical 100,000 program and erase cycles.
Table 1. Additional Feature Comparison
Additional
Featu-
res
Part Name
MX25L1605D
Protection and Security
Flexible
Block
protection
(BP0-BP3)
V
512-bit
secured OTP
Read
Performance
2 I/O Read
(50MHz)
Device ID
(command :
AB hex)
14 (hex)
Identifier
Device ID
(command :
90 hex)
C2 14 (hex)
(if ADD=0)
C2 15 (hex)
(if ADD=0)
Device ID
(command :
EF hex)
C2 14 (hex)
(if ADD=0)
C2 15 (hex)
(if ADD=0)
RDID
(command:
9F hex)
C2 20 15 (hex)
V
V
MX25L3205D
V
V
V
15 (hex)
C2 20 16 (hex)
MX25L6405D
V
V
V
16 (hex)
C2 16 (hex)
(if ADD=0)
C2 16 (hex)
(if ADD=0)
C2 20 17 (hex)
P/N: PM1290
3
REV. 1.4, OCT. 01, 2008
MCNIX [ MACRONIX INTERNATIONAL ]
