MX25L1605D
MX25L3205D
MX25L6405D
DATA PROTECTION
The MX25L1605D/3205D/6405D is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transition. During power up the device automatically resets the
state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only
occurs after successful completion of specific command sequences. The device also incorporates several features to
prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
•
Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and
tPUW (internal timer) may protect the Flash.
• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte
boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other
command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Continuously Program mode (CP) instruction completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
- Write Read-lock Bit (WRLB) instruction completion
•
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing
all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command
(RES).
Advanced Security Features: there are some protection and securuity features which protect content from inadvertent
write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read
only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible
which may protect various area by setting value of BP0-BP3 bits.
Please refer to table of "protected area sizes".
- The Hardware Proteced Mode (HPM) use WP#/ACC to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.
•
P/N: PM1290
6
REV. 1.4, OCT. 01, 2008
MCNIX [ MACRONIX INTERNATIONAL ]
